Index: fd.c =================================================================== RCS file: /cvsroot/syssrc/sys/arch/sparc/dev/fd.c,v retrieving revision 1.67 diff -c -r1.67 fd.c *** fd.c 1999/03/24 05:51:10 1.67 --- fd.c 2000/02/03 16:54:21 *************** *** 1,6 **** ! /* $NetBSD: fd.c,v 1.67 1999/03/24 05:51:10 mrg Exp $ */ /*- * Copyright (c) 1993, 1994, 1995 Charles M. Hannum. * Copyright (c) 1995 Paul Kranenburg. * Copyright (c) 1990 The Regents of the University of California. --- 1,42 ---- ! /* $NetBSD: fd.c,v 1.75 2000/01/28 15:46:20 pk Exp $ */ /*- + * Copyright (c) 2000 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Paul Kranenburg. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + /*- * Copyright (c) 1993, 1994, 1995 Charles M. Hannum. * Copyright (c) 1995 Paul Kranenburg. * Copyright (c) 1990 The Regents of the University of California. *************** *** 81,87 **** /* XXX misuse a flag to identify format operation */ #define B_FORMAT B_XXX - #define b_cylin b_resid #define FD_DEBUG #ifdef FD_DEBUG --- 117,122 ---- *************** *** 90,117 **** enum fdc_state { DEVIDLE = 0, ! MOTORWAIT, ! DOSEEK, ! SEEKWAIT, ! SEEKTIMEDOUT, ! SEEKCOMPLETE, ! DOIO, ! IOCOMPLETE, ! IOTIMEDOUT, ! DORESET, ! RESETCOMPLETE, ! RESETTIMEDOUT, ! DORECAL, ! RECALWAIT, ! RECALTIMEDOUT, ! RECALCOMPLETE, }; /* software state, per controller */ struct fdc_softc { struct device sc_dev; /* boilerplate */ bus_space_tag_t sc_bustag; ! caddr_t sc_reg; struct fd_softc *sc_fd[4]; /* pointers to children */ TAILQ_HEAD(drivehead, fd_softc) sc_drives; enum fdc_state sc_state; --- 125,154 ---- enum fdc_state { DEVIDLE = 0, ! MOTORWAIT, /* 1 */ ! DOSEEK, /* 2 */ ! SEEKWAIT, /* 3 */ ! SEEKTIMEDOUT, /* 4 */ ! SEEKCOMPLETE, /* 5 */ ! DOIO, /* 6 */ ! IOCOMPLETE, /* 7 */ ! IOTIMEDOUT, /* 8 */ ! IOCLEANUPWAIT, /* 9 */ ! IOCLEANUPTIMEDOUT,/*10 */ ! DORESET, /* 11 */ ! RESETCOMPLETE, /* 12 */ ! RESETTIMEDOUT, /* 13 */ ! DORECAL, /* 14 */ ! RECALWAIT, /* 15 */ ! RECALTIMEDOUT, /* 16 */ ! RECALCOMPLETE, /* 17 */ }; /* software state, per controller */ struct fdc_softc { struct device sc_dev; /* boilerplate */ bus_space_tag_t sc_bustag; ! struct fd_softc *sc_fd[4]; /* pointers to children */ TAILQ_HEAD(drivehead, fd_softc) sc_drives; enum fdc_state sc_state; *************** *** 119,133 **** #define FDC_82077 0x01 #define FDC_NEEDHEADSETTLE 0x02 #define FDC_EIS 0x04 int sc_errors; /* number of retries so far */ int sc_overruns; /* number of DMA overruns */ int sc_cfg; /* current configuration */ struct fdcio sc_io; #define sc_reg_msr sc_io.fdcio_reg_msr #define sc_reg_fifo sc_io.fdcio_reg_fifo #define sc_reg_dor sc_io.fdcio_reg_dor #define sc_reg_drs sc_io.fdcio_reg_msr ! #define sc_istate sc_io.fdcio_istate #define sc_data sc_io.fdcio_data #define sc_tc sc_io.fdcio_tc #define sc_nstat sc_io.fdcio_nstat --- 156,173 ---- #define FDC_82077 0x01 #define FDC_NEEDHEADSETTLE 0x02 #define FDC_EIS 0x04 + #define FDC_NEEDMOTORWAIT 0x08 int sc_errors; /* number of retries so far */ int sc_overruns; /* number of DMA overruns */ int sc_cfg; /* current configuration */ struct fdcio sc_io; + #define sc_handle sc_io.fdcio_handle #define sc_reg_msr sc_io.fdcio_reg_msr #define sc_reg_fifo sc_io.fdcio_reg_fifo #define sc_reg_dor sc_io.fdcio_reg_dor #define sc_reg_drs sc_io.fdcio_reg_msr ! #define sc_itask sc_io.fdcio_itask ! #define sc_istatus sc_io.fdcio_istatus #define sc_data sc_io.fdcio_data #define sc_tc sc_io.fdcio_tc #define sc_nstat sc_io.fdcio_nstat *************** *** 135,140 **** --- 175,181 ---- #define sc_intrcnt sc_io.fdcio_intrcnt }; + #undef FDC_C_HANDLER #ifndef FDC_C_HANDLER extern struct fdcio *fdciop; #endif *************** *** 145,151 **** void fdcattach_mainbus __P((struct device *, struct device *, void *)); void fdcattach_obio __P((struct device *, struct device *, void *)); ! void fdcattach __P((struct fdc_softc *, int, struct bootpath *)); struct cfattach fdc_mainbus_ca = { sizeof(struct fdc_softc), fdcmatch_mainbus, fdcattach_mainbus --- 186,192 ---- void fdcattach_mainbus __P((struct device *, struct device *, void *)); void fdcattach_obio __P((struct device *, struct device *, void *)); ! void fdcattach __P((struct fdc_softc *, int)); struct cfattach fdc_mainbus_ca = { sizeof(struct fdc_softc), fdcmatch_mainbus, fdcattach_mainbus *************** *** 180,186 **** /* The order of entries in the following table is important -- BEWARE! */ struct fd_type fd_types[] = { ! { 18,2,36,2,0xff,0xcf,0x1b,0x6c,80,2880,1,FDC_500KBPS,0xf6,1, "1.44MB" }, /* 1.44MB diskette */ { 9,2,18,2,0xff,0xdf,0x2a,0x50,80,1440,1,FDC_250KBPS,0xf6,1, "720KB" }, /* 3.5" 720kB diskette */ { 9,2,18,2,0xff,0xdf,0x2a,0x50,40, 720,2,FDC_250KBPS,0xf6,1, "360KB/x" }, /* 360kB in 720kB drive */ { 8,2,16,3,0xff,0xdf,0x35,0x74,77,1232,1,FDC_500KBPS,0xf6,1, "1.2MB/NEC" } /* 1.2 MB japanese format */ --- 221,227 ---- /* The order of entries in the following table is important -- BEWARE! */ struct fd_type fd_types[] = { ! { 18,2,36,2,0xff,0xcf,0x1b,0x54,80,2880,1,FDC_500KBPS,0xf6,1, "1.44MB" }, /* 1.44MB diskette */ { 9,2,18,2,0xff,0xdf,0x2a,0x50,80,1440,1,FDC_250KBPS,0xf6,1, "720KB" }, /* 3.5" 720kB diskette */ { 9,2,18,2,0xff,0xdf,0x2a,0x50,40, 720,2,FDC_250KBPS,0xf6,1, "360KB/x" }, /* 360kB in 720kB drive */ { 8,2,16,3,0xff,0xdf,0x35,0x74,77,1232,1,FDC_500KBPS,0xf6,1, "1.2MB/NEC" } /* 1.2 MB japanese format */ *************** *** 212,218 **** TAILQ_ENTRY(fd_softc) sc_drivechain; int sc_ops; /* I/O ops since last switch */ ! struct buf sc_q; /* head of buf chain */ }; /* floppy driver configuration */ --- 253,259 ---- TAILQ_ENTRY(fd_softc) sc_drivechain; int sc_ops; /* I/O ops since last switch */ ! struct buf sc_q; /* pending I/O requests */ }; /* floppy driver configuration */ *************** *** 238,251 **** void fd_motor_off __P((void *arg)); void fd_motor_on __P((void *arg)); int fdcresult __P((struct fdc_softc *fdc)); ! int out_fdc __P((struct fdc_softc *fdc, u_char x)); void fdcstart __P((struct fdc_softc *fdc)); ! void fdcstatus __P((struct device *dv, int n, char *s)); void fdc_reset __P((struct fdc_softc *fdc)); void fdctimeout __P((void *arg)); void fdcpseudointr __P((void *arg)); #ifdef FDC_C_HANDLER ! int fdchwintr __P((void *)); #else void fdchwintr __P((void)); #endif --- 279,292 ---- void fd_motor_off __P((void *arg)); void fd_motor_on __P((void *arg)); int fdcresult __P((struct fdc_softc *fdc)); ! int fdc_wrfifo __P((struct fdc_softc *fdc, u_char x)); void fdcstart __P((struct fdc_softc *fdc)); ! void fdcstatus __P((struct fdc_softc *fdc, char *s)); void fdc_reset __P((struct fdc_softc *fdc)); void fdctimeout __P((void *arg)); void fdcpseudointr __P((void *arg)); #ifdef FDC_C_HANDLER ! int fdc_c_hwintr __P((void *)); #else void fdchwintr __P((void)); #endif *************** *** 256,263 **** int fdformat __P((dev_t, struct ne7_fd_formb *, struct proc *)); void fd_do_eject __P((struct fd_softc *)); void fd_mountroot_hook __P((struct device *)); ! static void fdconf __P((struct fdc_softc *)); #if PIL_FDSOFT == 4 #define IE_FDSOFT IE_L4 #else --- 297,312 ---- int fdformat __P((dev_t, struct ne7_fd_formb *, struct proc *)); void fd_do_eject __P((struct fd_softc *)); void fd_mountroot_hook __P((struct device *)); ! static int fdconf __P((struct fdc_softc *)); ! static void establish_chip_type __P(( ! struct fdc_softc *, ! bus_space_tag_t, ! bus_type_t, ! bus_addr_t, ! bus_size_t, ! bus_space_handle_t)); + #if PIL_FDSOFT == 4 #define IE_FDSOFT IE_L4 #else *************** *** 273,279 **** ienab_bis(IE_L4); \ } while(0) #else ! #define AUDIO_SET_SWINTR ienab_bis(IE_FDSOFT) #endif /* defined(SUN4M) */ #endif /* FDC_C_HANDLER */ --- 322,328 ---- ienab_bis(IE_L4); \ } while(0) #else ! #define FD_SET_SWINTR ienab_bis(IE_FDSOFT) #endif /* defined(SUN4M) */ #endif /* FDC_C_HANDLER */ *************** *** 334,345 **** NULL, NULL)); } /* * Arguments passed between fdcattach and fdprobe. */ struct fdc_attach_args { int fa_drive; - struct bootpath *fa_bootpath; struct fd_type *fa_deftype; }; --- 383,446 ---- NULL, NULL)); } + static void + establish_chip_type(fdc, tag, type, addr, size, handle) + struct fdc_softc *fdc; + bus_space_tag_t tag; + bus_type_t type; + bus_addr_t addr; + bus_size_t size; + bus_space_handle_t handle; + { + u_int8_t v; + + /* + * This hack from Chris Torek: apparently DOR really + * addresses MSR/DRS on a 82072. + * We used to rely on the VERSION command to tell the + * difference (which did not work). + */ + + /* First, check the size of the register bank */ + if (size < 8) + /* It isn't a 82077 */ + return; + + /* Then probe the DOR register offset */ + if (bus_space_probe(tag, type, addr, + 1, /* probe size */ + FDREG77_DOR, /* offset */ + 0, /* flags */ + NULL, NULL) == 0) { + + /* It isn't a 82077 */ + return; + } + + v = bus_space_read_1(tag, handle, FDREG77_DOR); + if (v == NE7_RQM) { + /* + * Value in DOR looks like it's really MSR + */ + bus_space_write_1(tag, handle, FDREG77_DOR, FDC_250KBPS); + v = bus_space_read_1(tag, handle, FDREG77_DOR); + if (v == NE7_RQM) { + /* + * The value in the DOR didn't stick; + * it isn't a 82077 + */ + return; + } + } + + fdc->sc_flags |= FDC_82077; + } + /* * Arguments passed between fdcattach and fdprobe. */ struct fdc_attach_args { int fa_drive; struct fd_type *fa_deftype; }; *************** *** 362,375 **** return (QUIET); } ! static void fdconf(fdc) struct fdc_softc *fdc; { int vroom; ! if (out_fdc(fdc, NE7CMD_DUMPREG) || fdcresult(fdc) != 10) ! return; /* * dumpreg[7] seems to be a motor-off timeout; set it to whatever --- 463,480 ---- return (QUIET); } ! /* ! * Configure several parameters and features on the FDC. ! * Return 0 on success. ! */ ! static int fdconf(fdc) struct fdc_softc *fdc; { int vroom; ! if (fdc_wrfifo(fdc, NE7CMD_DUMPREG) || fdcresult(fdc) != 10) ! return (-1); /* * dumpreg[7] seems to be a motor-off timeout; set it to whatever *************** *** 379,396 **** vroom = 0x64; /* Configure controller to use FIFO and Implied Seek */ ! out_fdc(fdc, NE7CMD_CFG); ! out_fdc(fdc, vroom); ! out_fdc(fdc, fdc->sc_cfg); ! out_fdc(fdc, 0); /* PRETRK */ ! /* No result phase */ ! } ! /* ! * Controller and drives are represented by one and the same ! * Openprom node, so we can as well check for the floppy boots here. ! */ void fdcattach_mainbus(parent, self, aux) struct device *parent, *self; --- 484,520 ---- vroom = 0x64; /* Configure controller to use FIFO and Implied Seek */ ! if (fdc_wrfifo(fdc, NE7CMD_CFG) != 0) ! return (-1); ! if (fdc_wrfifo(fdc, vroom) != 0) ! return (-1); ! if (fdc_wrfifo(fdc, fdc->sc_cfg) != 0) ! return (-1); ! if (fdc_wrfifo(fdc, 0) != 0) /* PRETRK */ ! return (-1); ! /* No result phase for the NE7CMD_CFG command */ ! if ((fdc->sc_flags & FDC_82077) != 0) { ! /* Lock configuration across soft resets. */ ! if (fdc_wrfifo(fdc, NE7CMD_LOCK | CFG_LOCK) != 0 || ! fdcresult(fdc) != 1) { ! #ifdef DEBUG ! printf("fdconf: CFGLOCK failed"); ! #endif ! return (-1); ! } ! } + return (0); + #if 0 + if (fdc_wrfifo(fdc, NE7CMD_VERSION) == 0 && + fdcresult(fdc) == 1 && fdc->sc_status[0] == 0x90) { + if (fdc_debug) + printf("[version cmd]"); + } + #endif + } + void fdcattach_mainbus(parent, self, aux) struct device *parent, *self; *************** *** 398,411 **** { struct fdc_softc *fdc = (void *)self; struct mainbus_attach_args *ma = aux; - struct bootpath *bp; fdc->sc_bustag = ma->ma_bustag; if (ma->ma_promvaddr != 0) ! fdc->sc_reg = (caddr_t)ma->ma_promvaddr; else { - bus_space_handle_t bh; if (bus_space_map2( ma->ma_bustag, ma->ma_iospace, --- 522,533 ---- { struct fdc_softc *fdc = (void *)self; struct mainbus_attach_args *ma = aux; fdc->sc_bustag = ma->ma_bustag; if (ma->ma_promvaddr != 0) ! fdc->sc_handle = (bus_space_handle_t)ma->ma_promvaddr; else { if (bus_space_map2( ma->ma_bustag, ma->ma_iospace, *************** *** 413,443 **** ma->ma_size, BUS_SPACE_MAP_LINEAR, 0, ! &bh) != 0) { printf("%s: cannot map registers\n", self->dv_xname); return; } - fdc->sc_reg = (caddr_t)bh; } ! bp = NULL; ! if (ma->ma_bp != NULL && strcmp(ma->ma_bp->name, OBP_FDNAME) == 0) { ! int v0 = ma->ma_bp->val[0]; ! int v1 = ma->ma_bp->val[1]; ! /* ! * We can get the bootpath in several different ! * formats! The faked v1 bootpath looks like /fd@0,0. ! * The v2 bootpath is either just /fd0, in which case ! * `bp->val[0]' will have been set to -1, or /fd@x,y ! * where is the prom address specifier. ! */ ! if (((v0 == ma->ma_iospace) && (v1 == (int)ma->ma_paddr)) || ! ((v0 == -1) && (v1 == 0)) || /* v2: /fd0 */ ! ((v0 == 0) && (v1 == 0)) /* v1: /fd@0,0 */ ) ! bp = ma->ma_bp; ! } ! fdcattach(fdc, ma->ma_pri, bp); } void --- 535,554 ---- ma->ma_size, BUS_SPACE_MAP_LINEAR, 0, ! &fdc->sc_handle) != 0) { printf("%s: cannot map registers\n", self->dv_xname); return; } } ! establish_chip_type(fdc, ! ma->ma_bustag, ! ma->ma_iospace, ! ma->ma_paddr, ! ma->ma_size, ! fdc->sc_handle); ! fdcattach(fdc, ma->ma_pri); } void *************** *** 448,571 **** struct fdc_softc *fdc = (void *)self; union obio_attach_args *uoba = aux; struct sbus_attach_args *sa = &uoba->uoba_sbus; - struct bootpath *bp; fdc->sc_bustag = sa->sa_bustag; if (sa->sa_npromvaddrs != 0) ! fdc->sc_reg = (caddr_t)sa->sa_promvaddrs[0]; else { - bus_space_handle_t bh; - if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, sa->sa_offset, sa->sa_size, BUS_SPACE_MAP_LINEAR, 0, ! &bh) != 0) { printf("%s: cannot map control registers\n", self->dv_xname); return; } - fdc->sc_reg = (caddr_t)bh; } ! bp = NULL; ! if (sa->sa_bp != NULL && strcmp(sa->sa_bp->name, OBP_FDNAME) == 0) { ! int v0 = sa->sa_bp->val[0]; ! int v1 = sa->sa_bp->val[1]; ! /* ! * floppy controller on obio (such as on the sun4m), ! * e.g.: `/obio0/SUNW,fdtwo@0,700000'. ! * We use "slot, offset" to determine if this is the ! * right one. ! */ ! if ((v0 != sa->sa_slot) || (v1 != sa->sa_offset)) ! bp = sa->sa_bp; } ! fdcattach(fdc, sa->sa_pri, bp); } void ! fdcattach(fdc, pri, bp) struct fdc_softc *fdc; int pri; - struct bootpath *bp; { struct fdc_attach_args fa; char code; fdc->sc_state = DEVIDLE; ! fdc->sc_istate = ISTATE_IDLE; fdc->sc_flags |= FDC_EIS; TAILQ_INIT(&fdc->sc_drives); - - #ifdef FDC_C_HANDLER - (void)bus_intr_establish(fdc->sc_bustag, pri, 0, - fdchwintr, fdc); - #else - fdciop = &fdc->sc_io; - (void)bus_intr_establish(fdc->sc_bustag, pri, - BUS_INTR_ESTABLISH_FASTTRAP, - (int (*) __P((void *)))fdchwintr, NULL); - #endif - (void)bus_intr_establish(fdc->sc_bustag, PIL_FDSOFT, - BUS_INTR_ESTABLISH_SOFTINTR, - fdcswintr, fdc); - - /* Assume a 82077 */ - fdc->sc_reg_msr = &((struct fdreg_77 *)fdc->sc_reg)->fd_msr; - fdc->sc_reg_fifo = &((struct fdreg_77 *)fdc->sc_reg)->fd_fifo; - fdc->sc_reg_dor = &((struct fdreg_77 *)fdc->sc_reg)->fd_dor; ! code = '7'; ! if (*fdc->sc_reg_dor == NE7_RQM) { ! /* ! * This hack from Chris Torek: apparently DOR really ! * addresses MSR/DRS on a 82072. ! * We used to rely on the VERSION command to tell the ! * difference (which did not work). ! */ ! *fdc->sc_reg_dor = FDC_250KBPS; ! if (*fdc->sc_reg_dor == NE7_RQM) ! code = '2'; ! } ! if (code == '7') { ! fdc->sc_flags |= FDC_82077; } else { ! fdc->sc_reg_msr = &((struct fdreg_72 *)fdc->sc_reg)->fd_msr; ! fdc->sc_reg_fifo = &((struct fdreg_72 *)fdc->sc_reg)->fd_fifo; fdc->sc_reg_dor = 0; } ! #ifdef FD_DEBUG ! if (out_fdc(fdc, NE7CMD_VERSION) == 0 && ! fdcresult(fdc) == 1 && fdc->sc_status[0] == 0x90) { ! if (fdc_debug) ! printf("[version cmd]"); ! } ! #endif /* * Configure controller; enable FIFO, Implied seek, no POLL mode?. * Note: CFG_EFIFO is active-low, initial threshold value: 8 */ fdc->sc_cfg = CFG_EIS|/*CFG_EFIFO|*/CFG_POLL|(8 & CFG_THRHLD_MASK); ! fdconf(fdc); ! ! if (fdc->sc_flags & FDC_82077) { ! /* Lock configuration across soft resets. */ ! out_fdc(fdc, NE7CMD_LOCK | CFG_LOCK); ! if (fdcresult(fdc) != 1) ! printf(" CFGLOCK: unexpected response"); } - - evcnt_attach(&fdc->sc_dev, "intr", &fdc->sc_intrcnt); ! printf(" softpri %d: chip 8207%c\n", PIL_FDSOFT, code); ! fa.fa_bootpath = bp; /* physical limit: four drives per controller. */ for (fa.fa_drive = 0; fa.fa_drive < 4; fa.fa_drive++) { --- 559,651 ---- struct fdc_softc *fdc = (void *)self; union obio_attach_args *uoba = aux; struct sbus_attach_args *sa = &uoba->uoba_sbus; fdc->sc_bustag = sa->sa_bustag; if (sa->sa_npromvaddrs != 0) ! fdc->sc_handle = (bus_space_handle_t)sa->sa_promvaddrs[0]; else { if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, sa->sa_offset, sa->sa_size, BUS_SPACE_MAP_LINEAR, 0, ! &fdc->sc_handle) != 0) { printf("%s: cannot map control registers\n", self->dv_xname); return; } } ! establish_chip_type(fdc, ! sa->sa_bustag, ! sa->sa_slot, ! sa->sa_offset, ! sa->sa_size, ! fdc->sc_handle); ! ! if (strcmp(getpropstring(sa->sa_node, "status"), "disabled") == 0) { ! printf(": no drives attached\n"); ! return; } ! if (sa->sa_nintr != 0) ! fdcattach(fdc, sa->sa_pri); } void ! fdcattach(fdc, pri) struct fdc_softc *fdc; int pri; { struct fdc_attach_args fa; char code; fdc->sc_state = DEVIDLE; ! fdc->sc_itask = FDC_ITASK_NONE; ! fdc->sc_istatus = FDC_ISTATUS_NONE; fdc->sc_flags |= FDC_EIS; TAILQ_INIT(&fdc->sc_drives); ! if ((fdc->sc_flags & FDC_82077) != 0) { ! fdc->sc_reg_msr = FDREG77_MSR; ! fdc->sc_reg_fifo = FDREG77_FIFO; ! fdc->sc_reg_dor = FDREG77_DOR; ! code = '7'; ! fdc->sc_flags |= FDC_NEEDMOTORWAIT; } else { ! fdc->sc_reg_msr = FDREG72_MSR; ! fdc->sc_reg_fifo = FDREG72_FIFO; fdc->sc_reg_dor = 0; + code = '2'; } ! printf(" softpri %d: chip 8207%c\n", PIL_FDSOFT, code); /* * Configure controller; enable FIFO, Implied seek, no POLL mode?. * Note: CFG_EFIFO is active-low, initial threshold value: 8 */ fdc->sc_cfg = CFG_EIS|/*CFG_EFIFO|*/CFG_POLL|(8 & CFG_THRHLD_MASK); ! if (fdconf(fdc) != 0) { ! printf("%s: no drives attached\n", fdc->sc_dev.dv_xname); ! return; } ! #ifdef FDC_C_HANDLER ! (void)bus_intr_establish(fdc->sc_bustag, pri, 0, ! fdc_c_hwintr, fdc); ! #else ! fdciop = &fdc->sc_io; ! (void)bus_intr_establish(fdc->sc_bustag, pri, ! BUS_INTR_ESTABLISH_FASTTRAP, ! (int (*) __P((void *)))fdchwintr, NULL); ! #endif ! (void)bus_intr_establish(fdc->sc_bustag, PIL_FDSOFT, ! BUS_INTR_ESTABLISH_SOFTINTR, ! fdcswintr, fdc); ! evcnt_attach(&fdc->sc_dev, "intr", &fdc->sc_intrcnt); /* physical limit: four drives per controller. */ for (fa.fa_drive = 0; fa.fa_drive < 4; fa.fa_drive++) { *************** *** 573,580 **** fa.fa_deftype = &fd_types[0]; /* XXX */ (void)config_found(&fdc->sc_dev, (void *)&fa, fdprint); } - - bootpath_store(1, NULL); } int --- 653,658 ---- *************** *** 584,589 **** --- 662,669 ---- void *aux; { struct fdc_softc *fdc = (void *)parent; + bus_space_tag_t t = fdc->sc_bustag; + bus_space_handle_t h = fdc->sc_handle; struct fdc_attach_args *fa = aux; int drive = fa->fa_drive; int n, ok; *************** *** 592,615 **** /* XXX - for now, punt on more than one drive */ return (0); ! if (fdc->sc_flags & FDC_82077) { /* select drive and turn on motor */ ! *fdc->sc_reg_dor = drive | FDO_FRST | FDO_MOEN(drive); /* wait for motor to spin up */ delay(250000); } else { auxregbisc(AUXIO4C_FDS, 0); } fdc->sc_nstat = 0; ! out_fdc(fdc, NE7CMD_RECAL); ! out_fdc(fdc, drive); ! /* wait for recalibrate */ for (n = 0; n < 10000; n++) { delay(1000); ! if ((*fdc->sc_reg_msr & (NE7_RQM|NE7_DIO|NE7_CB)) == NE7_RQM) { /* wait a bit longer till device *really* is ready */ delay(100000); ! if (out_fdc(fdc, NE7CMD_SENSEI)) break; if (fdcresult(fdc) == 1 && fdc->sc_status[0] == 0x80) /* --- 672,700 ---- /* XXX - for now, punt on more than one drive */ return (0); ! if ((fdc->sc_flags & FDC_82077) != 0) { /* select drive and turn on motor */ ! bus_space_write_1(t, h, fdc->sc_reg_dor, ! drive | FDO_FRST | FDO_MOEN(drive)); /* wait for motor to spin up */ delay(250000); } else { auxregbisc(AUXIO4C_FDS, 0); } fdc->sc_nstat = 0; ! fdc_wrfifo(fdc, NE7CMD_RECAL); ! fdc_wrfifo(fdc, drive); ! ! /* Wait for recalibration to complete */ for (n = 0; n < 10000; n++) { + u_int8_t v; + delay(1000); ! v = bus_space_read_1(t, h, fdc->sc_reg_msr); ! if ((v & (NE7_RQM|NE7_DIO|NE7_CB)) == NE7_RQM) { /* wait a bit longer till device *really* is ready */ delay(100000); ! if (fdc_wrfifo(fdc, NE7CMD_SENSEI)) break; if (fdcresult(fdc) == 1 && fdc->sc_status[0] == 0x80) /* *************** *** 634,642 **** ok = (n == 2 && (fdc->sc_status[0] & 0xf8) == 0x20) ? 1 : 0; /* turn off motor */ ! if (fdc->sc_flags & FDC_82077) { /* deselect drive and turn motor off */ ! *fdc->sc_reg_dor = FDO_FRST | FDO_DS; } else { auxregbisc(0, AUXIO4C_FDS); } --- 719,727 ---- ok = (n == 2 && (fdc->sc_status[0] & 0xf8) == 0x20) ? 1 : 0; /* turn off motor */ ! if ((fdc->sc_flags & FDC_82077) != 0) { /* deselect drive and turn motor off */ ! bus_space_write_1(t, h, fdc->sc_reg_dor, FDO_FRST | FDO_DS); } else { auxregbisc(0, AUXIO4C_FDS); } *************** *** 671,679 **** fd->sc_deftype = type; fdc->sc_fd[drive] = fd; ! out_fdc(fdc, NE7CMD_SPECIFY); ! out_fdc(fdc, type->steprate); ! out_fdc(fdc, 6 | NE7_SPECIFY_NODMA); /* * Initialize and attach the disk structure. --- 756,765 ---- fd->sc_deftype = type; fdc->sc_fd[drive] = fd; ! fdc_wrfifo(fdc, NE7CMD_SPECIFY); ! fdc_wrfifo(fdc, type->steprate); ! /* XXX head load time == 6ms */ ! fdc_wrfifo(fdc, 6 | NE7_SPECIFY_NODMA); /* * Initialize and attach the disk structure. *************** *** 683,694 **** disk_attach(&fd->sc_dk); /* - * We're told if we're the boot device in fdcattach(). - */ - if (fa->fa_bootpath) - fa->fa_bootpath->dev = &fd->sc_dv; - - /* * Establish a mountroot_hook anyway in case we booted * with RB_ASKNAME and get selected as the boot device. */ --- 769,774 ---- *************** *** 756,775 **** bp->b_bcount = sz << DEV_BSHIFT; } ! bp->b_cylin = (bp->b_blkno * DEV_BSIZE) / (FD_BSIZE(fd) * fd->sc_type->seccyl); #ifdef FD_DEBUG if (fdc_debug > 1) printf("fdstrategy: b_blkno %d b_bcount %ld blkno %d cylin %ld\n", ! bp->b_blkno, bp->b_bcount, fd->sc_blkno, bp->b_cylin); #endif /* Queue transfer on drive, activate drive and controller if idle. */ s = splbio(); disksort(&fd->sc_q, bp); untimeout(fd_motor_off, fd); /* a good idea */ ! if (!fd->sc_q.b_active) fdstart(fd); #ifdef DIAGNOSTIC else { --- 836,855 ---- bp->b_bcount = sz << DEV_BSHIFT; } ! bp->b_cylinder = (bp->b_blkno * DEV_BSIZE) / (FD_BSIZE(fd) * fd->sc_type->seccyl); #ifdef FD_DEBUG if (fdc_debug > 1) printf("fdstrategy: b_blkno %d b_bcount %ld blkno %d cylin %ld\n", ! bp->b_blkno, bp->b_bcount, fd->sc_blkno, bp->b_cylinder); #endif /* Queue transfer on drive, activate drive and controller if idle. */ s = splbio(); disksort(&fd->sc_q, bp); untimeout(fd_motor_off, fd); /* a good idea */ ! if (fd->sc_q.b_active == 0) fdstart(fd); #ifdef DIAGNOSTIC else { *************** *** 822,828 **** if (fd->sc_drivechain.tqe_next && ++fd->sc_ops >= 8) { fd->sc_ops = 0; TAILQ_REMOVE(&fdc->sc_drives, fd, sc_drivechain); ! if (bp->b_actf) { TAILQ_INSERT_TAIL(&fdc->sc_drives, fd, sc_drivechain); } else fd->sc_q.b_active = 0; --- 902,908 ---- if (fd->sc_drivechain.tqe_next && ++fd->sc_ops >= 8) { fd->sc_ops = 0; TAILQ_REMOVE(&fdc->sc_drives, fd, sc_drivechain); ! if (bp->b_actf != NULL) { TAILQ_INSERT_TAIL(&fdc->sc_drives, fd, sc_drivechain); } else fd->sc_q.b_active = 0; *************** *** 841,856 **** fdc_reset(fdc) struct fdc_softc *fdc; { ! if (fdc->sc_flags & FDC_82077) { ! *fdc->sc_reg_dor = FDO_FDMAEN | FDO_MOEN(0); } ! *fdc->sc_reg_drs = DRS_RESET; delay(10); ! *fdc->sc_reg_drs = 0; ! if (fdc->sc_flags & FDC_82077) { ! *fdc->sc_reg_dor = FDO_FRST | FDO_FDMAEN | FDO_DS; } #ifdef FD_DEBUG if (fdc_debug) --- 921,941 ---- fdc_reset(fdc) struct fdc_softc *fdc; { ! bus_space_tag_t t = fdc->sc_bustag; ! bus_space_handle_t h = fdc->sc_handle; ! ! if ((fdc->sc_flags & FDC_82077) != 0) { ! bus_space_write_1(t, h, fdc->sc_reg_dor, ! FDO_FDMAEN | FDO_MOEN(0)); } ! bus_space_write_1(t, h, fdc->sc_reg_drs, DRS_RESET); delay(10); ! bus_space_write_1(t, h, fdc->sc_reg_drs, 0); ! if ((fdc->sc_flags & FDC_82077) != 0) { ! bus_space_write_1(t, h, fdc->sc_reg_dor, ! FDO_FRST | FDO_FDMAEN | FDO_DS); } #ifdef FD_DEBUG if (fdc_debug) *************** *** 866,872 **** u_char status; int n; ! if (fdc->sc_flags & FDC_82077) { status = FDO_FRST | FDO_FDMAEN; if ((fd = fdc->sc_drives.tqh_first) != NULL) status |= fd->sc_drive; --- 951,957 ---- u_char status; int n; ! if ((fdc->sc_flags & FDC_82077) != 0) { status = FDO_FRST | FDO_FDMAEN; if ((fd = fdc->sc_drives.tqh_first) != NULL) status |= fd->sc_drive; *************** *** 874,891 **** for (n = 0; n < 4; n++) if ((fd = fdc->sc_fd[n]) && (fd->sc_flags & FD_MOTOR)) status |= FDO_MOEN(n); ! *fdc->sc_reg_dor = status; } else { - int on = 0; ! for (n = 0; n < 4; n++) ! if ((fd = fdc->sc_fd[n]) && (fd->sc_flags & FD_MOTOR)) ! on = 1; ! if (on) { ! auxregbisc(AUXIO4C_FDS, 0); ! } else { ! auxregbisc(0, AUXIO4C_FDS); } } } --- 959,976 ---- for (n = 0; n < 4; n++) if ((fd = fdc->sc_fd[n]) && (fd->sc_flags & FD_MOTOR)) status |= FDO_MOEN(n); ! bus_space_write_1(fdc->sc_bustag, fdc->sc_handle, ! fdc->sc_reg_dor, status); } else { ! for (n = 0; n < 4; n++) { ! if ((fd = fdc->sc_fd[n]) != NULL && ! (fd->sc_flags & FD_MOTOR) != 0) { ! auxregbisc(AUXIO4C_FDS, 0); ! return; ! } } + auxregbisc(0, AUXIO4C_FDS); } } *************** *** 917,961 **** splx(s); } int fdcresult(fdc) struct fdc_softc *fdc; { ! u_char i; ! int j = 100000, ! n = 0; ! ! for (; j; j--) { ! i = *fdc->sc_reg_msr & (NE7_DIO | NE7_RQM | NE7_CB); ! if (i == NE7_RQM) return (fdc->sc_nstat = n); ! if (i == (NE7_DIO | NE7_RQM | NE7_CB)) { if (n >= sizeof(fdc->sc_status)) { log(LOG_ERR, "fdcresult: overrun\n"); return (-1); } ! fdc->sc_status[n++] = *fdc->sc_reg_fifo; } else ! delay(10); } log(LOG_ERR, "fdcresult: timeout\n"); return (fdc->sc_nstat = -1); } int ! out_fdc(fdc, x) struct fdc_softc *fdc; ! u_char x; { ! int i = 100000; ! ! while (((*fdc->sc_reg_msr & (NE7_DIO|NE7_RQM)) != NE7_RQM) && i-- > 0) delay(1); ! if (i <= 0) ! return (-1); ! ! *fdc->sc_reg_fifo = x; ! return (0); } int --- 1002,1063 ---- splx(s); } + /* + * Get status bytes off the FDC after a command has finished + * Returns the number of status bytes read; -1 on error. + * The return value is also stored in `sc_nstat'. + */ int fdcresult(fdc) struct fdc_softc *fdc; { ! bus_space_tag_t t = fdc->sc_bustag; ! bus_space_handle_t h = fdc->sc_handle; ! int j, n = 0; ! ! for (j = 10000; j; j--) { ! u_int8_t v = bus_space_read_1(t, h, fdc->sc_reg_msr); ! v &= (NE7_DIO | NE7_RQM | NE7_CB); ! if (v == NE7_RQM) return (fdc->sc_nstat = n); ! if (v == (NE7_DIO | NE7_RQM | NE7_CB)) { if (n >= sizeof(fdc->sc_status)) { log(LOG_ERR, "fdcresult: overrun\n"); return (-1); } ! fdc->sc_status[n++] = ! bus_space_read_1(t, h, fdc->sc_reg_fifo); } else ! delay(1); } + log(LOG_ERR, "fdcresult: timeout\n"); return (fdc->sc_nstat = -1); } + /* + * Write a command byte to the FDC. + * Returns 0 on success; -1 on failure (i.e. timeout) + */ int ! fdc_wrfifo(fdc, x) struct fdc_softc *fdc; ! u_int8_t x; { ! bus_space_tag_t t = fdc->sc_bustag; ! bus_space_handle_t h = fdc->sc_handle; ! int i; ! ! for (i = 100000; i-- > 0;) { ! u_int8_t v = bus_space_read_1(t, h, fdc->sc_reg_msr); ! if ((v & (NE7_DIO|NE7_RQM)) == NE7_RQM) { ! /* The chip is ready */ ! bus_space_write_1(t, h, fdc->sc_reg_fifo, x); ! return (0); ! } delay(1); ! } ! return (-1); } int *************** *** 972,978 **** if (unit >= fd_cd.cd_ndevs) return (ENXIO); fd = fd_cd.cd_devs[unit]; ! if (fd == 0) return (ENXIO); type = fd_dev_to_type(fd, dev); if (type == NULL) --- 1074,1080 ---- if (unit >= fd_cd.cd_ndevs) return (ENXIO); fd = fd_cd.cd_devs[unit]; ! if (fd == NULL) return (ENXIO); type = fd_dev_to_type(fd, dev); if (type == NULL) *************** *** 1073,1101 **** } void ! fdcstatus(dv, n, s) ! struct device *dv; ! int n; char *s; { ! struct fdc_softc *fdc = (void *)dv->dv_parent; char bits[64]; #if 0 /* * A 82072 seems to return on * gratuitous Sense Interrupt commands. */ ! if (n == 0 && (fdc->sc_flags & FDC_82077)) { ! out_fdc(fdc, NE7CMD_SENSEI); (void) fdcresult(fdc); n = 2; } #endif - - /* Just print last status */ - n = fdc->sc_nstat; ! printf("%s: %s: state %d", dv->dv_xname, s, fdc->sc_state); switch (n) { case 0: --- 1175,1205 ---- } void ! fdcstatus(fdc, s) ! struct fdc_softc *fdc; char *s; { ! struct fd_softc *fd = fdc->sc_drives.tqh_first; ! int n; char bits[64]; + + /* Just print last status */ + n = fdc->sc_nstat; + #if 0 /* * A 82072 seems to return on * gratuitous Sense Interrupt commands. */ ! if (n == 0 && (fdc->sc_flags & FDC_82077) != 0) { ! fdc_wrfifo(fdc, NE7CMD_SENSEI); (void) fdcresult(fdc); n = 2; } #endif ! printf("%s: %s: state %d", ! fd ? fd->sc_dv.dv_xname : "fdc", s, fdc->sc_state); switch (n) { case 0: *************** *** 1129,1147 **** void *arg; { struct fdc_softc *fdc = arg; ! struct fd_softc *fd = fdc->sc_drives.tqh_first; int s; s = splbio(); ! fdcstatus(&fd->sc_dv, 0, "timeout"); ! if (fd->sc_q.b_actf) fdc->sc_state++; else fdc->sc_state = DEVIDLE; (void) fdcstate(fdc); splx(s); } void --- 1233,1260 ---- void *arg; { struct fdc_softc *fdc = arg; ! struct fd_softc *fd; int s; s = splbio(); ! fd = fdc->sc_drives.tqh_first; ! if (fd == NULL) { ! printf("%s: timeout but no I/O pending: state %d, istatus=%d\n", ! fdc->sc_dev.dv_xname, ! fdc->sc_state, fdc->sc_istatus); ! fdc->sc_state = DEVIDLE; ! goto out; ! } ! if (fd->sc_q.b_actf != NULL) fdc->sc_state++; else fdc->sc_state = DEVIDLE; (void) fdcstate(fdc); + out: splx(s); + } void *************** *** 1164,1219 **** * (in-window) handler. */ int ! fdchwintr(arg) void *arg; { struct fdc_softc *fdc = arg; ! switch (fdc->sc_istate) { ! case ISTATE_IDLE: return (0); ! case ISTATE_SENSEI: ! out_fdc(fdc, NE7CMD_SENSEI); ! fdcresult(fdc); ! fdc->sc_istate = ISTATE_IDLE; FD_SET_SWINTR; return (1); ! case ISTATE_SPURIOUS: ! fdcresult(fdc); ! fdc->sc_istate = ISTATE_SPURIOUS; ! printf("fdc: stray hard interrupt... "); ! FD_SET_SWINTR; ! return (1); ! case ISTATE_DMA: break; default: ! printf("fdc: goofed ...\n"); return (1); } for (;;) { ! register int msr; ! msr = *fdc->sc_reg_msr; if ((msr & NE7_RQM) == 0) break; if ((msr & NE7_NDM) == 0) { fdcresult(fdc); ! fdc->sc_istate = ISTATE_IDLE; ! ienab_bis(IE_FDSOFT); printf("fdc: overrun: tc = %d\n", fdc->sc_tc); break; } ! if (msr & NE7_DIO) { ! *fdc->sc_data++ = *fdc->sc_reg_fifo; ! } else { ! *fdc->sc_reg_fifo = *fdc->sc_data++; ! } if (--fdc->sc_tc == 0) { ! fdc->sc_istate = ISTATE_DONE; FTC_FLIP; fdcresult(fdc); FD_SET_SWINTR; --- 1277,1340 ---- * (in-window) handler. */ int ! fdc_c_hwintr(arg) void *arg; { struct fdc_softc *fdc = arg; + bus_space_tag_t t = fdc->sc_bustag; + bus_space_handle_t h = fdc->sc_handle; ! switch (fdc->sc_itask) { ! case FDC_ITASK_NONE: return (0); ! case FDC_ITASK_SENSI: ! if (fdc_wrfifo(fdc, NE7CMD_SENSEI) != 0 || fdcresult(fdc) != 0) ! fdc->sc_istatus = FDC_ISTATUS_ERROR; ! else ! fdc->sc_istatus = FDC_ISTATUS_DONE; FD_SET_SWINTR; return (1); ! case FDC_ITASK_DMA: ! /* Proceed with pseudo-dma below */ break; default: ! printf("fdc: stray hard interrupt: itask=%d\n", fdc->sc_itask); ! fdc->sc_istatus = FDC_ISTATUS_SPURIOUS; ! FD_SET_SWINTR; return (1); } + /* + * Pseudo DMA in progress + */ for (;;) { ! u_int8_t msr; ! msr = bus_space_read_1(t, h, fdc->sc_reg_msr); if ((msr & NE7_RQM) == 0) + /* That's all this round */ break; if ((msr & NE7_NDM) == 0) { fdcresult(fdc); ! fdc->sc_istatus = FDC_ISTATUS_DONE; ! FD_SET_SWINTR; printf("fdc: overrun: tc = %d\n", fdc->sc_tc); break; } ! /* Another byte can be transferred */ ! if ((msr & NE7_DIO) != 0) ! *fdc->sc_data = ! bus_space_read_1(t, h, fdc->sc_reg_fifo); ! else ! bus_space_write_1(t, h, fdc->sc_reg_fifo, ! *fdc->sc_data); ! ! fdc->sc_data++; if (--fdc->sc_tc == 0) { ! fdc->sc_istatus = FDC_ISTATUS_DONE; FTC_FLIP; fdcresult(fdc); FD_SET_SWINTR; *************** *** 1231,1240 **** struct fdc_softc *fdc = arg; int s; ! if (fdc->sc_istate != ISTATE_DONE) return (0); - fdc->sc_istate = ISTATE_IDLE; s = splbio(); fdcstate(fdc); splx(s); --- 1352,1370 ---- struct fdc_softc *fdc = arg; int s; ! if (fdc->sc_istatus == FDC_ISTATUS_NONE) ! /* This (software) interrupt is not for us */ return (0); + + switch (fdc->sc_istatus) { + case FDC_ISTATUS_ERROR: + printf("fdc: ierror status: state %d\n", fdc->sc_state); + break; + case FDC_ISTATUS_SPURIOUS: + printf("fdc: spurious interrupt: state %d\n", fdc->sc_state); + break; + } s = splbio(); fdcstate(fdc); splx(s); *************** *** 1248,1255 **** #define st0 fdc->sc_status[0] #define st1 fdc->sc_status[1] #define cyl fdc->sc_status[1] ! #define OUT_FDC(fdc, c, s) \ ! do { if (out_fdc(fdc, (c))) { (fdc)->sc_state = (s); goto loop; } } while(0) struct fd_softc *fd; struct buf *bp; --- 1378,1388 ---- #define st0 fdc->sc_status[0] #define st1 fdc->sc_status[1] #define cyl fdc->sc_status[1] ! #define FDC_WRFIFO(fdc, c) do { \ ! if (fdc_wrfifo(fdc, (c))) { \ ! goto xxx; \ ! } \ ! } while(0) struct fd_softc *fd; struct buf *bp; *************** *** 1257,1274 **** struct fd_type *type; struct ne7_fd_formb *finfo = NULL; ! if (fdc->sc_istate != ISTATE_IDLE) { ! /* Trouble... */ ! printf("fdc: spurious interrupt: state %d, istate=%d\n", ! fdc->sc_state, fdc->sc_istate); ! fdc->sc_istate = ISTATE_IDLE; ! if (fdc->sc_state == RESETCOMPLETE || ! fdc->sc_state == RESETTIMEDOUT) { ! panic("fdcintr: spurious interrupt can't be cleared"); ! } ! goto doreset; ! } loop: /* Is there a drive for the controller to do a transfer with? */ --- 1390,1401 ---- struct fd_type *type; struct ne7_fd_formb *finfo = NULL; + if (fdc->sc_istatus == FDC_ISTATUS_ERROR) + fdc->sc_state = DORESET; ! /* Clear I task/status field */ ! fdc->sc_istatus = FDC_ISTATUS_NONE; ! fdc->sc_itask = FDC_ITASK_NONE; loop: /* Is there a drive for the controller to do a transfer with? */ *************** *** 1311,1317 **** fd->sc_flags |= FD_MOTOR | FD_MOTOR_WAIT; fd_set_motor(fdc); fdc->sc_state = MOTORWAIT; ! if (fdc->sc_flags & FDC_82077) { /* XXX */ /* Allow .25s for motor to stabilize. */ timeout(fd_motor_on, fd, hz / 4); } else { --- 1438,1444 ---- fd->sc_flags |= FD_MOTOR | FD_MOTOR_WAIT; fd_set_motor(fdc); fdc->sc_state = MOTORWAIT; ! if ((fdc->sc_flags & FDC_NEEDMOTORWAIT) != 0) { /*XXX*/ /* Allow .25s for motor to stabilize. */ timeout(fd_motor_on, fd, hz / 4); } else { *************** *** 1328,1361 **** doseek: if ((fdc->sc_flags & FDC_EIS) && (bp->b_flags & B_FORMAT) == 0) { ! fd->sc_cylin = bp->b_cylin; /* We use implied seek */ goto doio; } ! if (fd->sc_cylin == bp->b_cylin) goto doio; - /* specify command */ - OUT_FDC(fdc, NE7CMD_SPECIFY, SEEKTIMEDOUT); - OUT_FDC(fdc, fd->sc_type->steprate, SEEKTIMEDOUT); - /* XXX head load time == 6ms */ - OUT_FDC(fdc, 6 | NE7_SPECIFY_NODMA, SEEKTIMEDOUT); - - fdc->sc_istate = ISTATE_SENSEI; - /* seek function */ - OUT_FDC(fdc, NE7CMD_SEEK, SEEKTIMEDOUT); - OUT_FDC(fdc, fd->sc_drive, SEEKTIMEDOUT); /* drive number */ - OUT_FDC(fdc, bp->b_cylin * fd->sc_type->step, SEEKTIMEDOUT); - fd->sc_cylin = -1; fdc->sc_state = SEEKWAIT; fdc->sc_nstat = 0; fd->sc_dk.dk_seek++; - disk_busy(&fd->sc_dk); timeout(fdctimeout, fdc, 4 * hz); return (1); case DOIO: --- 1455,1488 ---- doseek: if ((fdc->sc_flags & FDC_EIS) && (bp->b_flags & B_FORMAT) == 0) { ! fd->sc_cylin = bp->b_cylinder; /* We use implied seek */ goto doio; } ! if (fd->sc_cylin == bp->b_cylinder) goto doio; fd->sc_cylin = -1; fdc->sc_state = SEEKWAIT; fdc->sc_nstat = 0; fd->sc_dk.dk_seek++; + disk_busy(&fd->sc_dk); timeout(fdctimeout, fdc, 4 * hz); + + /* specify command */ + FDC_WRFIFO(fdc, NE7CMD_SPECIFY); + FDC_WRFIFO(fdc, fd->sc_type->steprate); + /* XXX head load time == 6ms */ + FDC_WRFIFO(fdc, 6 | NE7_SPECIFY_NODMA); + + fdc->sc_itask = FDC_ITASK_SENSEI; + /* seek function */ + FDC_WRFIFO(fdc, NE7CMD_SEEK); + FDC_WRFIFO(fdc, fd->sc_drive); /* drive number */ + FDC_WRFIFO(fdc, bp->b_cylinder * fd->sc_type->step); return (1); case DOIO: *************** *** 1388,1430 **** fdc->sc_data = bp->b_data + fd->sc_skip; fdc->sc_tc = fd->sc_nbytes; ! *fdc->sc_reg_drs = type->rate; #ifdef FD_DEBUG if (fdc_debug > 1) ! printf("fdcintr: %s drive %d track %d head %d sec %d nblks %d\n", ! read ? "read" : "write", fd->sc_drive, ! fd->sc_cylin, head, sec, nblks); #endif fdc->sc_state = IOCOMPLETE; ! fdc->sc_istate = ISTATE_DMA; fdc->sc_nstat = 0; if (finfo != NULL) { /* formatting */ ! OUT_FDC(fdc, NE7CMD_FORMAT, IOTIMEDOUT); ! OUT_FDC(fdc, (head << 2) | fd->sc_drive, IOTIMEDOUT); ! OUT_FDC(fdc, finfo->fd_formb_secshift, IOTIMEDOUT); ! OUT_FDC(fdc, finfo->fd_formb_nsecs, IOTIMEDOUT); ! OUT_FDC(fdc, finfo->fd_formb_gaplen, IOTIMEDOUT); ! OUT_FDC(fdc, finfo->fd_formb_fillbyte, IOTIMEDOUT); } else { if (read) ! OUT_FDC(fdc, NE7CMD_READ, IOTIMEDOUT); else ! OUT_FDC(fdc, NE7CMD_WRITE, IOTIMEDOUT); ! OUT_FDC(fdc, (head << 2) | fd->sc_drive, IOTIMEDOUT); ! OUT_FDC(fdc, fd->sc_cylin, IOTIMEDOUT); /*track*/ ! OUT_FDC(fdc, head, IOTIMEDOUT); ! OUT_FDC(fdc, sec + 1, IOTIMEDOUT); /*sector+1*/ ! OUT_FDC(fdc, type->secsize, IOTIMEDOUT);/*sector size*/ ! OUT_FDC(fdc, type->sectrac, IOTIMEDOUT);/*secs/track*/ ! OUT_FDC(fdc, type->gap1, IOTIMEDOUT); /*gap1 size*/ ! OUT_FDC(fdc, type->datalen, IOTIMEDOUT);/*data length*/ } - disk_busy(&fd->sc_dk); - - /* allow 2 seconds for operation */ - timeout(fdctimeout, fdc, 2 * hz); return (1); /* will return later */ case SEEKWAIT: --- 1515,1562 ---- fdc->sc_data = bp->b_data + fd->sc_skip; fdc->sc_tc = fd->sc_nbytes; ! bus_space_write_1(fdc->sc_bustag, fdc->sc_handle, ! fdc->sc_reg_drs, type->rate); #ifdef FD_DEBUG if (fdc_debug > 1) ! printf("fdcstate: doio: %s drive %d " ! "track %d head %d sec %d nblks %d\n", ! finfo ? "format" : ! (read ? "read" : "write"), ! fd->sc_drive, fd->sc_cylin, head, sec, nblks); #endif fdc->sc_state = IOCOMPLETE; ! fdc->sc_itask = FDC_ITASK_DMA; fdc->sc_nstat = 0; + + disk_busy(&fd->sc_dk); + + /* allow 3 seconds for operation */ + timeout(fdctimeout, fdc, 3 * hz); + if (finfo != NULL) { /* formatting */ ! FDC_WRFIFO(fdc, NE7CMD_FORMAT); ! FDC_WRFIFO(fdc, (head << 2) | fd->sc_drive); ! FDC_WRFIFO(fdc, finfo->fd_formb_secshift); ! FDC_WRFIFO(fdc, finfo->fd_formb_nsecs); ! FDC_WRFIFO(fdc, finfo->fd_formb_gaplen); ! FDC_WRFIFO(fdc, finfo->fd_formb_fillbyte); } else { if (read) ! FDC_WRFIFO(fdc, NE7CMD_READ); else ! FDC_WRFIFO(fdc, NE7CMD_WRITE); ! FDC_WRFIFO(fdc, (head << 2) | fd->sc_drive); ! FDC_WRFIFO(fdc, fd->sc_cylin); /*track*/ ! FDC_WRFIFO(fdc, head); ! FDC_WRFIFO(fdc, sec + 1); /*sector+1*/ ! FDC_WRFIFO(fdc, type->secsize);/*sector size*/ ! FDC_WRFIFO(fdc, type->sectrac);/*secs/track*/ ! FDC_WRFIFO(fdc, type->gap1); /*gap1 size*/ ! FDC_WRFIFO(fdc, type->datalen);/*data length*/ } return (1); /* will return later */ case SEEKWAIT: *************** *** 1441,1464 **** /* Make sure seek really happened. */ if (fdc->sc_nstat != 2 || (st0 & 0xf8) != 0x20 || ! cyl != bp->b_cylin * fd->sc_type->step) { #ifdef FD_DEBUG if (fdc_debug) ! fdcstatus(&fd->sc_dv, 2, "seek failed"); #endif fdcretry(fdc); goto loop; } ! fd->sc_cylin = bp->b_cylin; goto doio; case IOTIMEDOUT: FTC_FLIP; ! (void)fdcresult(fdc); ! /*FALLTHROUGH*/ case SEEKTIMEDOUT: case RECALTIMEDOUT: case RESETTIMEDOUT: fdcretry(fdc); goto loop; --- 1573,1619 ---- /* Make sure seek really happened. */ if (fdc->sc_nstat != 2 || (st0 & 0xf8) != 0x20 || ! cyl != bp->b_cylinder * fd->sc_type->step) { #ifdef FD_DEBUG if (fdc_debug) ! fdcstatus(fdc, "seek failed"); #endif fdcretry(fdc); goto loop; } ! fd->sc_cylin = bp->b_cylinder; goto doio; case IOTIMEDOUT: + /* + * Try to abort the I/O operation without resetting + * the chip first. Poke TC and arrange to pick up + * the timed out I/O command's status. + */ + fdc->sc_itask = FDC_ITASK_RESULT; + fdc->sc_state = IOCLEANUPWAIT; + fdc->sc_nstat = 0; + /* 1/10 second should be enough */ + timeout(fdctimeout, fdc, hz/10); FTC_FLIP; ! return (1); ! ! case IOCLEANUPTIMEDOUT: case SEEKTIMEDOUT: case RECALTIMEDOUT: case RESETTIMEDOUT: + fdcstatus(fdc, "timeout"); + + /* All other timeouts always roll through to a chip reset */ + fdcretry(fdc); + + /* Force reset, no matter what fdcretry() says */ + fdc->sc_state = DORESET; + goto loop; + + case IOCLEANUPWAIT: /* IO FAILED, cleanup succeeded */ + untimeout(fdctimeout, fdc); + disk_unbusy(&fd->sc_dk, (bp->b_bcount - bp->b_resid)); fdcretry(fdc); goto loop; *************** *** 1472,1478 **** ((st0 & 0xf8) != 0x20 || (fdc->sc_cfg & CFG_EIS) == 0))) { #ifdef FD_DEBUG if (fdc_debug) { ! fdcstatus(&fd->sc_dv, 7, bp->b_flags & B_READ ? "read failed" : "write failed"); printf("blkno %d nblks %d nstat %d tc %d\n", --- 1627,1633 ---- ((st0 & 0xf8) != 0x20 || (fdc->sc_cfg & CFG_EIS) == 0))) { #ifdef FD_DEBUG if (fdc_debug) { ! fdcstatus(fdc, bp->b_flags & B_READ ? "read failed" : "write failed"); printf("blkno %d nblks %d nstat %d tc %d\n", *************** *** 1533,1569 **** fd->sc_skip += fd->sc_nbytes; fd->sc_bcount -= fd->sc_nbytes; if (finfo == NULL && fd->sc_bcount > 0) { ! bp->b_cylin = fd->sc_blkno / fd->sc_type->seccyl; goto doseek; } fdfinish(fd, bp); goto loop; case DORESET: - doreset: /* try a reset, keep motor on */ fd_set_motor(fdc); delay(100); - fdc_reset(fdc); fdc->sc_nstat = 0; ! fdc->sc_istate = ISTATE_SENSEI; fdc->sc_state = RESETCOMPLETE; timeout(fdctimeout, fdc, hz / 2); return (1); /* will return later */ case RESETCOMPLETE: untimeout(fdctimeout, fdc); fdconf(fdc); ! /* fall through */ case DORECAL: fdc->sc_state = RECALWAIT; ! fdc->sc_istate = ISTATE_SENSEI; fdc->sc_nstat = 0; - /* recalibrate function */ - OUT_FDC(fdc, NE7CMD_RECAL, RECALTIMEDOUT); - OUT_FDC(fdc, fd->sc_drive, RECALTIMEDOUT); timeout(fdctimeout, fdc, 5 * hz); return (1); /* will return later */ case RECALWAIT: --- 1688,1723 ---- fd->sc_skip += fd->sc_nbytes; fd->sc_bcount -= fd->sc_nbytes; if (finfo == NULL && fd->sc_bcount > 0) { ! bp->b_cylinder = fd->sc_blkno / fd->sc_type->seccyl; goto doseek; } fdfinish(fd, bp); goto loop; case DORESET: /* try a reset, keep motor on */ fd_set_motor(fdc); delay(100); fdc->sc_nstat = 0; ! fdc->sc_itask = FDC_ITASK_SENSEI; fdc->sc_state = RESETCOMPLETE; timeout(fdctimeout, fdc, hz / 2); + fdc_reset(fdc); return (1); /* will return later */ case RESETCOMPLETE: untimeout(fdctimeout, fdc); fdconf(fdc); ! /* FALLTHROUGH */ case DORECAL: fdc->sc_state = RECALWAIT; ! fdc->sc_itask = FDC_ITASK_SENSEI; fdc->sc_nstat = 0; timeout(fdctimeout, fdc, 5 * hz); + /* recalibrate function */ + FDC_WRFIFO(fdc, NE7CMD_RECAL); + FDC_WRFIFO(fdc, fd->sc_drive); return (1); /* will return later */ case RECALWAIT: *************** *** 1579,1585 **** if (fdc->sc_nstat != 2 || (st0 & 0xf8) != 0x20 || cyl != 0) { #ifdef FD_DEBUG if (fdc_debug) ! fdcstatus(&fd->sc_dv, 2, "recalibrate failed"); #endif fdcretry(fdc); goto loop; --- 1733,1739 ---- if (fdc->sc_nstat != 2 || (st0 & 0xf8) != 0x20 || cyl != 0) { #ifdef FD_DEBUG if (fdc_debug) ! fdcstatus(fdc, "recalibrate failed"); #endif fdcretry(fdc); goto loop; *************** *** 1593,1604 **** goto doseek; default: ! fdcstatus(&fd->sc_dv, 0, "stray interrupt"); return (1); } #ifdef DIAGNOSTIC panic("fdcintr: impossible"); #endif #undef st0 #undef st1 #undef cyl --- 1747,1769 ---- goto doseek; default: ! fdcstatus(fdc, "stray interrupt"); return (1); } #ifdef DIAGNOSTIC panic("fdcintr: impossible"); #endif + + xxx: + /* + * We get here if the chip locks up in FDC_WRFIFO() + * Cancel any operation and schedule a reset + */ + untimeout(fdctimeout, fdc); + fdcretry(fdc); + (fdc)->sc_state = DORESET; + goto loop; + #undef st0 #undef st1 #undef cyl *************** *** 1608,1616 **** fdcretry(fdc) struct fdc_softc *fdc; { - char bits[64]; struct fd_softc *fd; struct buf *bp; fd = fdc->sc_drives.tqh_first; bp = fd->sc_q.b_actf; --- 1773,1781 ---- fdcretry(fdc) struct fdc_softc *fdc; { struct fd_softc *fd; struct buf *bp; + int error = EIO; fd = fdc->sc_drives.tqh_first; bp = fd->sc_q.b_actf; *************** *** 1621,1626 **** --- 1786,1798 ---- switch (fdc->sc_errors) { case 0: + if (fdc->sc_nstat == 7 && + (fdc->sc_status[0] & 0xd8) == 0x40 && + (fdc->sc_status[1] & 0x2) == 0x2) { + printf("%s: read-only medium\n", fd->sc_dv.dv_xname); + error = EROFS; + goto failsilent; + } /* try again */ fdc->sc_state = (fdc->sc_flags & FDC_EIS) ? DOIO : DOSEEK; *************** *** 1632,1637 **** --- 1804,1824 ---- break; case 4: + if (fdc->sc_nstat == 7 && + fdc->sc_status[0] == 0 && + fdc->sc_status[1] == 0 && + fdc->sc_status[2] == 0) { + /* + * We've retried a few times and we've got + * valid status and all three status bytes + * are zero. Assume this condition is the + * result of no disk loaded into the drive. + */ + printf("%s: no medium?\n", fd->sc_dv.dv_xname); + error = ENODEV; + goto failsilent; + } + /* still no go; reset the bastard */ fdc->sc_state = DORESET; break; *************** *** 1642,1661 **** diskerr(bp, "fd", "hard error", LOG_PRINTF, fd->sc_skip / FD_BSIZE(fd), (struct disklabel *)NULL); ! ! printf(" (st0 %s", bitmask_snprintf(fdc->sc_status[0], ! NE7_ST0BITS, bits, sizeof(bits))); ! printf(" st1 %s", bitmask_snprintf(fdc->sc_status[1], ! NE7_ST1BITS, bits, sizeof(bits))); ! printf(" st2 %s", bitmask_snprintf(fdc->sc_status[2], ! NE7_ST2BITS, bits, sizeof(bits))); ! printf(" cyl %d head %d sec %d)\n", ! fdc->sc_status[3], fdc->sc_status[4], ! fdc->sc_status[5]); } bp->b_flags |= B_ERROR; ! bp->b_error = EIO; fdfinish(fd, bp); } fdc->sc_errors++; --- 1829,1841 ---- diskerr(bp, "fd", "hard error", LOG_PRINTF, fd->sc_skip / FD_BSIZE(fd), (struct disklabel *)NULL); ! printf("\n"); ! fdcstatus(fdc, "controller status"); } + failsilent: bp->b_flags |= B_ERROR; ! bp->b_error = error; fdfinish(fd, bp); } fdc->sc_errors++; *************** *** 1690,1703 **** int flag; struct proc *p; { ! struct fd_softc *fd = fd_cd.cd_devs[FDUNIT(dev)]; struct fdformat_parms *form_parms; struct fdformat_cmd *form_cmd; struct ne7_fd_formb fd_formb; int il[FD_MAX_NSEC + 1]; int i, j; int error; switch (cmd) { case DIOCGDINFO: *(struct disklabel *)addr = *(fd->sc_dk.dk_label); --- 1870,1892 ---- int flag; struct proc *p; { ! struct fd_softc *fd; ! struct fdc_softc *fdc; struct fdformat_parms *form_parms; struct fdformat_cmd *form_cmd; struct ne7_fd_formb fd_formb; int il[FD_MAX_NSEC + 1]; + int unit; int i, j; int error; + unit = FDUNIT(dev); + if (unit >= fd_cd.cd_ndevs) + return (ENXIO); + + fd = fd_cd.cd_devs[FDUNIT(dev)]; + fdc = (struct fdc_softc *)fd->sc_dv.dv_parent; + switch (cmd) { case DIOCGDINFO: *(struct disklabel *)addr = *(fd->sc_dk.dk_label); *************** *** 1867,1906 **** fd->sc_opts = *(int *)addr; return (0); ! #ifdef DEBUG case _IO('f', 100): ! { ! int i; ! struct fdc_softc *fdc = (struct fdc_softc *) ! fd->sc_dv.dv_parent; ! ! out_fdc(fdc, NE7CMD_DUMPREG); fdcresult(fdc); ! printf("dumpreg(%d regs): <", fdc->sc_nstat); for (i = 0; i < fdc->sc_nstat; i++) printf(" 0x%x", fdc->sc_status[i]); printf(">\n"); - } - return (0); case _IOW('f', 101, int): ! ((struct fdc_softc *)fd->sc_dv.dv_parent)->sc_cfg &= ! ~CFG_THRHLD_MASK; ! ((struct fdc_softc *)fd->sc_dv.dv_parent)->sc_cfg |= ! (*(int *)addr & CFG_THRHLD_MASK); ! fdconf((struct fdc_softc *) fd->sc_dv.dv_parent); return (0); case _IO('f', 102): ! { ! int i; ! struct fdc_softc *fdc = (struct fdc_softc *) ! fd->sc_dv.dv_parent; ! out_fdc(fdc, NE7CMD_SENSEI); fdcresult(fdc); ! printf("sensei(%d regs): <", fdc->sc_nstat); for (i=0; i< fdc->sc_nstat; i++) printf(" 0x%x", fdc->sc_status[i]); - } printf(">\n"); return (0); #endif --- 2056,2083 ---- fd->sc_opts = *(int *)addr; return (0); ! #ifdef FD_DEBUG case _IO('f', 100): ! fdc_wrfifo(fdc, NE7CMD_DUMPREG); fdcresult(fdc); ! printf("fdc: dumpreg(%d regs): <", fdc->sc_nstat); for (i = 0; i < fdc->sc_nstat; i++) printf(" 0x%x", fdc->sc_status[i]); printf(">\n"); return (0); + case _IOW('f', 101, int): ! fdc->sc_cfg &= ~CFG_THRHLD_MASK; ! fdc->sc_cfg |= (*(int *)addr & CFG_THRHLD_MASK); ! fdconf(fdc); return (0); + case _IO('f', 102): ! fdc_wrfifo(fdc, NE7CMD_SENSEI); fdcresult(fdc); ! printf("fdc: sensei(%d regs): <", fdc->sc_nstat); for (i=0; i< fdc->sc_nstat; i++) printf(" 0x%x", fdc->sc_status[i]); printf(">\n"); return (0); #endif *************** *** 1947,1955 **** bp->b_data = (caddr_t)finfo; #ifdef FD_DEBUG ! if (fdc_debug) printf("fdformat: blkno 0x%x count %ld\n", bp->b_blkno, bp->b_bcount); #endif /* now do the format */ --- 2124,2151 ---- bp->b_data = (caddr_t)finfo; #ifdef FD_DEBUG ! if (fdc_debug) { ! int i; ! printf("fdformat: blkno 0x%x count %ld\n", bp->b_blkno, bp->b_bcount); + + printf("\tcyl:\t%d\n", finfo->cyl); + printf("\thead:\t%d\n", finfo->head); + printf("\tnsecs:\t%d\n", finfo->fd_formb_nsecs); + printf("\tsshft:\t%d\n", finfo->fd_formb_secshift); + printf("\tgaplen:\t%d\n", finfo->fd_formb_gaplen); + printf("\ttrack data:"); + for (i = 0; i < finfo->fd_formb_nsecs; i++) { + printf(" [c%d h%d s%d]", + finfo->fd_formb_cylno(i), + finfo->fd_formb_headno(i), + finfo->fd_formb_secno(i) ); + if (finfo->fd_formb_secsize(i) != 2) + printf("", finfo->fd_formb_secsize(i)); + } + printf("\n"); + } #endif /* now do the format */ *************** *** 1995,2000 **** --- 2191,2197 ---- lp->d_nsectors = fd->sc_type->sectrac; lp->d_ncylinders = fd->sc_type->cylinders; lp->d_ntracks = fd->sc_type->heads; /* Go figure... */ + lp->d_secperunit = lp->d_secpercyl * lp->d_ncylinders; lp->d_rpm = 3600; /* XXX like it matters... */ strncpy(lp->d_typename, "floppy", sizeof(lp->d_typename)); *************** *** 2051,2061 **** auxregbisc(AUXIO4C_FEJ, AUXIO4C_FDS); return; } ! if (CPU_ISSUN4M && (fdc->sc_flags & FDC_82077)) { ! int dor = FDO_FRST | FDO_FDMAEN | FDO_MOEN(0); ! *fdc->sc_reg_dor = dor | FDO_EJ; delay(10); ! *fdc->sc_reg_dor = FDO_FRST | FDO_DS; return; } } --- 2248,2261 ---- auxregbisc(AUXIO4C_FEJ, AUXIO4C_FDS); return; } ! if (CPU_ISSUN4M && (fdc->sc_flags & FDC_82077) != 0) { ! bus_space_tag_t t = fdc->sc_bustag; ! bus_space_handle_t h = fdc->sc_handle; ! u_int8_t dor = FDO_FRST | FDO_FDMAEN | FDO_MOEN(0); ! ! bus_space_write_1(t, h, fdc->sc_reg_dor, dor | FDO_EJ); delay(10); ! bus_space_write_1(t, h, fdc->sc_reg_dor, FDO_FRST | FDO_DS); return; } } Index: fdreg.h =================================================================== RCS file: /cvsroot/syssrc/sys/arch/sparc/dev/fdreg.h,v retrieving revision 1.6 diff -c -r1.6 fdreg.h *** fdreg.h 1997/05/02 13:03:44 1.6 --- fdreg.h 2000/02/03 16:54:21 *************** *** 1,4 **** ! /* $NetBSD: fdreg.h,v 1.6 1997/05/02 13:03:44 pk Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. --- 1,4 ---- ! /* $NetBSD: fdreg.h,v 1.7 2000/01/17 16:57:15 pk Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. *************** *** 42,74 **** /* uses NEC765 controller */ #include ! #ifndef _LOCORE ! struct fdreg_77 { ! u_int8_t fd_statusA; ! u_int8_t fd_statusB; ! u_int8_t fd_dor; /* Digital Output Register (R/W) */ ! u_int8_t fd_tdr; /* Tape Control Register (R/W) */ ! u_int8_t fd_msr; /* Main Status Register (R) */ ! #define fd_drs fd_msr /* Data Rate Select Register (W) */ ! u_int8_t fd_fifo; /* Data (FIFO) register (R/W) */ ! u_int8_t fd_reserved; ! u_int8_t fd_dir; /* Digital Input Register (R) */ ! #define fd_ccr fd_dir /* Configuration Control (W) */ ! }; ! ! struct fdreg_72 { ! u_int8_t fd_msr; /* Main Status Register (R) */ ! #if already_a_define ! #define fd_drs fd_msr /* Data Rate Select Register (W) */ ! #endif ! u_int8_t fd_fifo; /* Data (FIFO) register (R/W) */ ! }; ! ! union fdreg { ! struct fdreg_72 fun72; ! struct fdreg_77 fun77; ! }; ! #endif /* Data Select Register bits */ #define DRS_RESET 0x80 --- 42,67 ---- /* uses NEC765 controller */ #include ! /* ! * Register offsets for the 82077 controller. ! */ ! #define FDREG77_STATUSA 0 ! #define FDREG77_STATUSB 1 ! #define FDREG77_DOR 2 /* Digital Output Register (R/W) */ ! #define FDREG77_TDR 3 /* Tape Control Register (R/W) */ ! #define FDREG77_MSR 4 /* Main Status Register (R) */ ! #define FDREG77_DRS 4 /* Data Rate Select Register (W) */ ! #define FDREG77_FIFO 5 /* Data (FIFO) register (R/W) */ ! #define FDREG77_DIR 7 /* Digital Input Register (R) */ ! #define FDREG77_CCR 7 /* Configuration Control (W) */ ! ! /* ! * Register offsets for the 82077 controller. ! */ ! #define FDREG72_MSR 0 /* Main Status Register (R) */ ! #define FDREG72_DRS 0 /* Data Rate Select Register (W) */ ! #define FDREG72_FIFO 1 /* Data (FIFO) register (R/W) */ ! /* Data Select Register bits */ #define DRS_RESET 0x80 Index: fdvar.h =================================================================== RCS file: /cvsroot/syssrc/sys/arch/sparc/dev/fdvar.h,v retrieving revision 1.8 diff -c -r1.8 fdvar.h *** fdvar.h 1998/09/05 15:42:42 1.8 --- fdvar.h 2000/02/03 16:54:21 *************** *** 1,4 **** ! /* $NetBSD: fdvar.h,v 1.8 1998/09/05 15:42:42 pk Exp $ */ /*- * Copyright (c) 1998 The NetBSD Foundation, Inc. --- 1,4 ---- ! /* $NetBSD: fdvar.h,v 1.10 2000/01/21 13:22:02 pk Exp $ */ /*- * Copyright (c) 1998 The NetBSD Foundation, Inc. *************** *** 43,60 **** #ifndef _LOCORE struct fdcio { /* * 82072 (sun4c) and 82077 (sun4m) controllers have different ! * register layout; so we cache some here. */ ! volatile u_int8_t *fdcio_reg_msr; ! volatile u_int8_t *fdcio_reg_fifo; ! volatile u_int8_t *fdcio_reg_dor; /* 82077 only */ /* * Interrupt state. */ ! int fdcio_istate; /* * IO state. --- 43,62 ---- #ifndef _LOCORE struct fdcio { + bus_space_handle_t fdcio_handle; /* * 82072 (sun4c) and 82077 (sun4m) controllers have different ! * register layout; so we cache offsets to the registers here. */ ! u_int fdcio_reg_msr; ! u_int fdcio_reg_fifo; ! u_int fdcio_reg_dor; /* 82077 only */ /* * Interrupt state. */ ! int fdcio_itask; ! int fdcio_istatus; /* * IO state. *************** *** 71,82 **** }; #endif /* _LOCORE */ ! /* istate values */ ! #define ISTATE_IDLE 0 /* No HW interrupt expected */ ! #define ISTATE_SPURIOUS 1 /* Spurious HW interrupt detected */ ! #define ISTATE_SENSEI 2 /* Do SENSEI on next HW interrupt */ ! #define ISTATE_DMA 3 /* Pseudo-DMA in progress */ ! #define ISTATE_DONE 4 /* Interrupt processing complete */ #define FD_MAX_NSEC 36 /* highest known number of spt - allow for */ --- 73,89 ---- }; #endif /* _LOCORE */ ! /* itask values */ ! #define FDC_ITASK_NONE 0 /* No HW interrupt expected */ ! #define FDC_ITASK_SENSEI 1 /* Do SENSEI on next HW interrupt */ ! #define FDC_ITASK_DMA 2 /* Do Pseudo-DMA */ ! #define FDC_ITASK_RESULT 3 /* Pick up command results */ ! ! /* istatus values */ ! #define FDC_ISTATUS_NONE 0 /* No status available */ ! #define FDC_ISTATUS_SPURIOUS 1 /* Spurious HW interrupt detected */ ! #define FDC_ISTATUS_ERROR 2 /* Operation completed abnormally */ ! #define FDC_ISTATUS_DONE 3 /* Operation completed normally */ #define FD_MAX_NSEC 36 /* highest known number of spt - allow for */