Index: sys/dev/ic/ath.c =================================================================== RCS file: /cvsroot/src/sys/dev/ic/ath.c,v retrieving revision 1.100 diff -u -r1.100 ath.c --- sys/dev/ic/ath.c 4 May 2008 20:02:06 -0000 1.100 +++ sys/dev/ic/ath.c 2 Jun 2008 00:18:46 -0000 @@ -253,10 +253,10 @@ static void ath_printrxbuf(struct ath_buf *bf, int); static void ath_printtxbuf(struct ath_buf *bf, int); #else -#define IFF_DUMPPKTS(sc, m) \ +#define IFF_DUMPPKTS(sc, m) \ ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) -#define DPRINTF(m, fmt, ...) -#define KEYPRINTF(sc, k, ix, mac) +#define DPRINTF(m, fmt, ...) +#define KEYPRINTF(sc, k, ix, mac) #endif MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); @@ -518,13 +518,28 @@ * separate key cache entries are required to * handle both tx+rx MIC keys. */ - if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) + if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) { ic->ic_caps |= IEEE80211_C_TKIPMIC; - if (ath_hal_tkipsplit(ah)) + /* + * Check if h/w does MIC correctly when + * WMM is turned on. + */ + if (ath_hal_wmetkipmic(ah)) + ic->ic_caps |= IEEE80211_C_WME_TKIPMIC; + } + + /* + * If the h/w supports storing tx+rx MIC keys + * in one cache slot automatically enable use. + */ + if (ath_hal_tkipsplit(ah) || + !ath_hal_settkipsplit(ah, AH_FALSE)) sc->sc_splitmic = 1; } sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); +#if 0 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); +#endif /* * TPC support can be done either with a global cap or * per-packet support. The latter is not available on @@ -661,6 +676,7 @@ void ath_suspend(struct ath_softc *sc) { +#if notyet /* * Set the chip in full sleep mode. Note that we are * careful to do this only when bringing the interface @@ -671,15 +687,22 @@ * issue with newer parts that go to sleep more quickly. */ ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); +#endif } bool ath_resume(struct ath_softc *sc) { - int i; struct ath_hal *ah = sc->sc_ah; + struct ieee80211com *ic = &sc->sc_ic; + HAL_STATUS status; + int i; +#if notyet ath_hal_setpower(ah, HAL_PM_AWAKE); +#else + ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status); +#endif /* * Reset the key cache since some parts do not @@ -877,6 +900,7 @@ static void ath_radar_proc(void *arg, int pending) { +#if 0 struct ath_softc *sc = arg; struct ifnet *ifp = &sc->sc_if; struct ath_hal *ah = sc->sc_ah; @@ -890,6 +914,7 @@ */ /* XXX not yet */ } +#endif } static u_int @@ -946,6 +971,17 @@ */ ath_stop_locked(ifp, 0); + int dummy; /* XXX: gcc */ + /* Whether we should enable h/w TKIP MIC */ + if ((ic->ic_caps & IEEE80211_C_WME) && + ((ic->ic_caps & IEEE80211_C_WME_TKIPMIC) || + !(ic->ic_flags & IEEE80211_F_WME))) { + dummy = ath_hal_settkipmic(ah, AH_TRUE); + } else { + dummy = ath_hal_settkipmic(ah, AH_FALSE); + } + + /* * The basic interface to setting the hardware in a good * state is ``reset''. On return the hardware is known to @@ -1450,21 +1486,36 @@ KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); - KASSERT(sc->sc_splitmic, ("key cache !split")); if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { - /* - * TX key goes at first index, RX key at the rx index. - * The hal handles the MIC keys at index+64. - */ - memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); - KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); - if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) - return 0; - - memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); - KEYPRINTF(sc, k->wk_keyix+32, hk, mac); - /* XXX delete tx key on failure? */ - return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); + if (sc->sc_splitmic) { + /* + * TX key goes at first index, RX key at the rx index. + * The hal handles the MIC keys at index+64. + */ + memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); + KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); + if (!ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, + zerobssid)) + return 0; + + memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); + KEYPRINTF(sc, k->wk_keyix+32, hk, mac); + /* XXX delete tx key on failure? */ + return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix+32), + hk, mac); + } else { + /* + * Room for both TX+RX MIC keys in one key cache + * slot, just set key at the first index; the HAL + * will handle the reset. + */ + memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); +#if HAL_ABI_VERSION > 0x06052200 + memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); +#endif + KEYPRINTF(sc, k->wk_keyix, hk, mac); + return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, mac); + } } else if (k->wk_flags & IEEE80211_KEY_XR) { /* * TX/RX key goes at first index. @@ -1473,7 +1524,7 @@ memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); KEYPRINTF(sc, k->wk_keyix, hk, mac); - return ath_hal_keyset(ah, k->wk_keyix, hk, mac); + return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, mac); } return 0; #undef IEEE80211_KEY_XR @@ -1532,13 +1583,12 @@ } else mac = mac0; - if (hk.kv_type == HAL_CIPHER_TKIP && - (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && - sc->sc_splitmic) { + if ((hk.kv_type == HAL_CIPHER_TKIP && + (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) && sc->sc_splitmic) { return ath_keyset_tkip(sc, k, &hk, mac); } else { KEYPRINTF(sc, k->wk_keyix, &hk, mac); - return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); + return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), &hk, mac); } #undef N } @@ -1590,11 +1640,11 @@ keyix+32, keyix+32+64); *txkeyix = keyix; *rxkeyix = keyix+32; - return 1; + return keyix; } } DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); - return 0; + return IEEE80211_KEYIX_NONE; #undef N } @@ -1813,6 +1863,8 @@ if (ic->ic_opmode != IEEE80211_M_HOSTAP && (ifp->if_flags & IFF_PROMISC)) rfilt |= HAL_RX_FILTER_PROM; + if (ifp->if_flags & IFF_PROMISC) + rfilt |= HAL_RX_FILTER_CONTROL | HAL_RX_FILTER_PROBEREQ; if (ic->ic_opmode == IEEE80211_M_STA || ic->ic_opmode == IEEE80211_M_IBSS || state == IEEE80211_S_SCAN) @@ -2750,7 +2802,7 @@ ds = bf->bf_desc; ds->ds_link = HTOAH32(bf->bf_daddr); /* link to self */ ds->ds_data = bf->bf_segs[0].ds_addr; - ds->ds_vdata = mtod(m, void *); /* for radar */ + /* ds->ds_vdata = mtod(m, void *); for radar */ ath_hal_setuprxdesc(ah, ds , m->m_len /* buffer size */ , 0 @@ -2848,6 +2900,21 @@ } static void +ath_handle_micerror(struct ieee80211com *ic, + struct ieee80211_frame *wh, int keyix) +{ + struct ieee80211_node *ni; + + /* XXX recheck MIC to deal w/ chips that lie */ + /* XXX discard MIC errors on !data frames */ + ni = ieee80211_find_rxnode_withkey(ic, (const struct ieee80211_frame_min *) wh, keyix); + if (ni != NULL) { + ieee80211_notify_michael_failure(ic, wh, keyix); + ieee80211_free_node(ni); + } +} + +static void ath_rx_proc(void *arg, int npending) { #define PA2DESC(_sc, _pa) \ @@ -2862,14 +2929,23 @@ struct mbuf *m; struct ieee80211_node *ni; struct ath_node *an; - int len, type, ngood; + int len, ngood, type; u_int phyerr; HAL_STATUS status; int16_t nf; u_int64_t tsf; + uint8_t rxerr_tap, rxerr_mon; NET_LOCK_GIANT(); /* XXX */ + rxerr_tap = + (ifp->if_flags & IFF_PROMISC) ? HAL_RXERR_CRC|HAL_RXERR_PHY : 0; + + if (sc->sc_ic.ic_opmode == IEEE80211_M_MONITOR) + rxerr_mon = HAL_RXERR_DECRYPT|HAL_RXERR_MIC; + else if (ifp->if_flags & IFF_PROMISC) + rxerr_tap |= HAL_RXERR_DECRYPT|HAL_RXERR_MIC; + DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); ngood = 0; nf = ath_hal_getchannoise(ah, &sc->sc_curchan); @@ -2903,7 +2979,8 @@ * a self-linked list to avoid rx overruns. */ status = ath_hal_rxprocdesc(ah, ds, - bf->bf_daddr, PA2DESC(sc, ds->ds_link)); + bf->bf_daddr, PA2DESC(sc, ds->ds_link), + tsf, &ds->ds_rxstat); #ifdef AR_DEBUG if (sc->sc_debug & ATH_DEBUG_RECV_DESC) ath_printrxbuf(bf, status == HAL_OK); @@ -2962,12 +3039,10 @@ bf->bf_dmamap, 0, bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); - ieee80211_notify_michael_failure(ic, + ath_handle_micerror(ic, mtod(m, struct ieee80211_frame *), sc->sc_splitmic ? - ds->ds_rxstat.rs_keyix-32 : - ds->ds_rxstat.rs_keyix - ); + ds->ds_rxstat.rs_keyix-32 : ds->ds_rxstat.rs_keyix); } } ifp->if_ierrors++; @@ -2976,9 +3051,8 @@ * to see them in monitor mode (in monitor mode * allow through packets that have crypto problems). */ - if ((ds->ds_rxstat.rs_status &~ - (HAL_RXERR_DECRYPT|HAL_RXERR_MIC)) || - sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) + + if (ds->ds_rxstat.rs_status &~ (rxerr_tap|rxerr_mon)) goto rx_next; } rx_accept: @@ -3020,6 +3094,11 @@ sc->sc_rx_th.wr_tsf = htole64( ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf)); sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; + if (ds->ds_rxstat.rs_status & + (HAL_RXERR_CRC|HAL_RXERR_PHY)) { + sc->sc_rx_th.wr_flags |= + IEEE80211_RADIOTAP_F_BADFCS; + } sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf; sc->sc_rx_th.wr_antnoise = nf; @@ -3030,6 +3109,10 @@ } #endif + if (ds->ds_rxstat.rs_status & rxerr_tap) { + m_freem(m); + goto rx_next; + } /* * From this point on we assume the frame is at least * as large as ieee80211_frame_min; verify that. @@ -3111,8 +3194,10 @@ /* rx signal state monitoring */ ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); +#if 0 if (ath_hal_radar_event(ah)) TASK_RUN_OR_ENQUEUE(&sc->sc_radartask); +#endif if (ngood) sc->sc_lastrx = tsf; @@ -3927,11 +4012,9 @@ } ds0 = &bf->bf_desc[0]; ds = &bf->bf_desc[bf->bf_nseg - 1]; - status = ath_hal_txprocdesc(ah, ds); -#ifdef AR_DEBUG + status = ath_hal_txprocdesc(ah, ds, &ds->ds_txstat); if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) ath_printtxbuf(bf, status == HAL_OK); -#endif if (status == HAL_EINPROGRESS) { ATH_TXQ_UNLOCK(txq); break; @@ -4103,6 +4186,7 @@ struct ath_hal *ah = sc->sc_ah; struct ieee80211_node *ni; struct ath_buf *bf; + struct ath_desc *ds; /* * NB: this assumes output has been stopped and @@ -4118,11 +4202,11 @@ } ATH_TXQ_REMOVE_HEAD(txq, bf_list); ATH_TXQ_UNLOCK(txq); -#ifdef AR_DEBUG + ds = &bf->bf_desc[bf->bf_nseg - 1]; if (sc->sc_debug & ATH_DEBUG_RESET) ath_printtxbuf(bf, - ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); -#endif /* AR_DEBUG */ + ath_hal_txprocdesc(ah, bf->bf_desc, + &ds->ds_txstat) == HAL_OK); bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); m_freem(bf->bf_m); bf->bf_m = NULL; @@ -4188,12 +4272,12 @@ ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) struct ath_hal *ah = sc->sc_ah; + u_int64_t tsf; ath_hal_stoppcurecv(ah); /* disable PCU */ ath_hal_setrxfilter(ah, 0); /* clear recv filter */ ath_hal_stopdmarecv(ah); /* disable DMA engine */ DELAY(3000); /* 3ms is long enough for 1 frame */ -#ifdef AR_DEBUG if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { struct ath_buf *bf; @@ -4201,13 +4285,14 @@ (void *)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { struct ath_desc *ds = bf->bf_desc; + tsf = ath_hal_gettsf64(sc->sc_ah); HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, - bf->bf_daddr, PA2DESC(sc, ds->ds_link)); + bf->bf_daddr, PA2DESC(sc, ds->ds_link), + tsf, &ds->ds_rxstat); if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) ath_printrxbuf(bf, status == HAL_OK); } } -#endif sc->sc_rxlink = NULL; /* just in case */ #undef PA2DESC } @@ -5025,7 +5110,7 @@ !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); } } -#endif /* AR_DEBUG */ +#endif /* AR_DEBUG */ static void ath_watchdog(struct ifnet *ifp) Index: sys/dev/ic/athvar.h =================================================================== RCS file: /cvsroot/src/sys/dev/ic/athvar.h,v retrieving revision 1.24 diff -u -r1.24 athvar.h --- sys/dev/ic/athvar.h 12 Mar 2008 18:02:21 -0000 1.24 +++ sys/dev/ic/athvar.h 2 Jun 2008 00:18:47 -0000 @@ -77,6 +77,12 @@ */ #define ATH_KEYMAX 128 /* max key cache size we handle */ #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ +/* + * Convert from net80211 layer values to Ath layer values. Hopefully this will + * be optimised away when the two constants are the same. + */ +typedef unsigned int ath_keyix_t; +#define ATH_KEY(_keyix) ((_keyix == IEEE80211_KEYIX_NONE) ? HAL_TXKEYIX_INVALID : _keyix) /* driver-specific node state */ struct ath_node { @@ -454,6 +460,12 @@ (*(_pcc) = (_ah)->ah_countryCode) #define ath_hal_tkipsplit(_ah) \ (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) +#define ath_hal_settkipmic(_ah, _v) \ + (ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) == HAL_OK) +#define ath_hal_settkipsplit(_ah, _v) \ + (ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) == HAL_OK) +#define ath_hal_wmetkipmic(_ah) \ + (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) #define ath_hal_hwphycounters(_ah) \ (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) #define ath_hal_hasdiversity(_ah) \ @@ -528,8 +540,8 @@ #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) -#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \ - ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0)) +#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, tsf, a5) \ + ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), (tsf), (a5))) #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ _txr0, _txtr0, _keyix, _ant, _flags, \ _rtsrate, _rtsdura) \ @@ -542,8 +554,8 @@ (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) -#define ath_hal_txprocdesc(_ah, _ds) \ - ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) +#define ath_hal_txprocdesc(_ah, _ds, _a2) \ + ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_a2))) #define ath_hal_gettxintrtxqs(_ah, _txqs) \ ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) Index: sys/contrib/dev/ath/ah.h =================================================================== RCS file: /cvsroot/src/sys/contrib/dev/ath/ah.h,v retrieving revision 1.4 diff -u -r1.4 ah.h --- sys/contrib/dev/ath/ah.h 5 Jun 2006 05:14:38 -0000 1.4 +++ sys/contrib/dev/ath/ah.h 2 Jun 2008 00:18:47 -0000 @@ -33,7 +33,7 @@ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGES. * - * $Id: ah.h,v 1.4 2006/06/05 05:14:38 gdamore Exp $ + * $Id: //depot/sw/branches/linux_hal/ah.h#4 $ */ #ifndef _ATH_AH_H_ @@ -131,6 +131,11 @@ HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ HAL_CAP_INTMIT = 29, /* interference mitigation */ + HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */ + HAL_CAP_HT = 31, /* hardware can support HT */ + HAL_CAP_NUMTXCHAIN = 32, /* # TX chains supported */ + HAL_CAP_NUMRXCHAIN = 33, /* # RX chains supported */ + HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */ } HAL_CAPABILITY_TYPE; /* @@ -286,8 +291,6 @@ /* compression definitions */ #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ #define HAL_COMP_BUF_ALIGN_SIZE 512 -#define HAL_DECOMP_MASK_SIZE 128 - /* * Transmit packet types. This belongs in ah_desc.h, but @@ -304,7 +307,8 @@ HAL_PKT_TYPE_BEACON = 3, HAL_PKT_TYPE_PROBE_RESP = 4, HAL_PKT_TYPE_CHIRP = 5, - HAL_PKT_TYPE_GRP_POLL = 6, + HAL_PKT_TYPE_GRP_POLL = 6, + HAL_PKT_TYPE_AMPDU = 7, } HAL_PKT_TYPE; /* Rx Filter Frame Types */ @@ -357,8 +361,10 @@ HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ HAL_INT_GPIO = 0x01000000, HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ + HAL_INT_CST = 0x10000000, /* Non-common mapping */ + HAL_INT_GTT = 0x20000000, /* Non-common mapping */ HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ - HAL_INT_GLOBAL = 0x80000000, /* Set/clear IER */ +#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ HAL_INT_BMISC = HAL_INT_TIM | HAL_INT_DTIM | HAL_INT_DTIMSYNC @@ -377,7 +383,6 @@ | HAL_INT_SWBA | HAL_INT_BMISS | HAL_INT_GPIO, - HAL_INT_NOCARD = 0xffffffff /* To signal the card was removed */ } HAL_INT; typedef enum { @@ -390,8 +395,8 @@ * Channels are specified by frequency. */ typedef struct { + u_int32_t channelFlags; /* see below */ u_int16_t channel; /* setting in Mhz */ - u_int16_t channelFlags; /* see below */ u_int8_t privFlags; int8_t maxRegTxPower; /* max regulatory tx power in dBm */ int8_t maxTxPower; /* max true tx power in 0.5 dBm */ @@ -399,18 +404,21 @@ } HAL_CHANNEL; /* channelFlags */ -#define CHANNEL_CW_INT 0x0002 /* CW interference detected on channel */ -#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ -#define CHANNEL_CCK 0x0020 /* CCK channel */ -#define CHANNEL_OFDM 0x0040 /* OFDM channel */ -#define CHANNEL_2GHZ 0x0080 /* 2 GHz spectrum channel. */ -#define CHANNEL_5GHZ 0x0100 /* 5 GHz spectrum channel */ -#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed in the channel */ -#define CHANNEL_DYN 0x0400 /* dynamic CCK-OFDM channel */ -#define CHANNEL_XR 0x0800 /* XR channel */ -#define CHANNEL_STURBO 0x2000 /* Static turbo, no 11a-only usage */ -#define CHANNEL_HALF 0x4000 /* Half rate channel */ -#define CHANNEL_QUARTER 0x8000 /* Quarter rate channel */ +#define CHANNEL_CW_INT 0x00002 /* CW interference detected on channel */ +#define CHANNEL_TURBO 0x00010 /* Turbo Channel */ +#define CHANNEL_CCK 0x00020 /* CCK channel */ +#define CHANNEL_OFDM 0x00040 /* OFDM channel */ +#define CHANNEL_2GHZ 0x00080 /* 2 GHz spectrum channel */ +#define CHANNEL_5GHZ 0x00100 /* 5 GHz spectrum channel */ +#define CHANNEL_PASSIVE 0x00200 /* Only passive scan allowed in the channel */ +#define CHANNEL_DYN 0x00400 /* dynamic CCK-OFDM channel */ +#define CHANNEL_XR 0x00800 /* XR channel */ +#define CHANNEL_STURBO 0x02000 /* Static turbo, no 11a-only usage */ +#define CHANNEL_HALF 0x04000 /* Half rate channel */ +#define CHANNEL_QUARTER 0x08000 /* Quarter rate channel */ +#define CHANNEL_HT20 0x10000 /* 11n 20MHZ channel */ +#define CHANNEL_HT40PLUS 0x20000 /* 11n 40MHZ channel w/ ext chan above */ +#define CHANNEL_HT40MINUS 0x40000 /* 11n 40MHZ channel w/ ext chan below */ /* privFlags */ #define CHANNEL_INTERFERENCE 0x01 /* Software use: channel interference @@ -433,8 +441,15 @@ #define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) #define CHANNEL_108A CHANNEL_T #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) +#define CHANNEL_G_HT20 (CHANNEL_G|CHANNEL_HT20) +#define CHANNEL_A_HT20 (CHANNEL_A|CHANNEL_HT20) +#define CHANNEL_G_HT40PLUS (CHANNEL_G|CHANNEL_HT40PLUS) +#define CHANNEL_G_HT40MINUS (CHANNEL_G|CHANNEL_HT40MINUS) +#define CHANNEL_A_HT40PLUS (CHANNEL_A|CHANNEL_HT40PLUS) +#define CHANNEL_A_HT40MINUS (CHANNEL_A|CHANNEL_HT40MINUS) #define CHANNEL_ALL \ - (CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ | CHANNEL_5GHZ | CHANNEL_TURBO) + (CHANNEL_OFDM | CHANNEL_CCK| CHANNEL_2GHZ | CHANNEL_5GHZ | \ + CHANNEL_TURBO | CHANNEL_HT20 | CHANNEL_HT40PLUS | CHANNEL_HT40MINUS) #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) #define HAL_ANTENNA_MIN_MODE 0 @@ -473,16 +488,22 @@ HAL_MODE_XR = 0x100, /* XR channels */ HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */ HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */ - HAL_MODE_ALL = 0xfff + HAL_MODE_11NG_HT20 = 0x008000, + HAL_MODE_11NA_HT20 = 0x010000, + HAL_MODE_11NG_HT40PLUS = 0x020000, + HAL_MODE_11NG_HT40MINUS = 0x040000, + HAL_MODE_11NA_HT40PLUS = 0x080000, + HAL_MODE_11NA_HT40MINUS = 0x100000, + HAL_MODE_ALL = 0xffffff }; typedef struct { int rateCount; /* NB: for proper padding */ - u_int8_t rateCodeToIndex[32]; /* back mapping */ - struct { + u_int8_t rateCodeToIndex[144]; /* back mapping */ + struct { u_int8_t valid; /* valid for rate control use */ u_int8_t phy; /* CCK/OFDM/XR */ - u_int16_t rateKbps; /* transfer rate in kbs */ + u_int32_t rateKbps; /* transfer rate in kbs */ u_int8_t rateCode; /* rate for h/w descriptors */ u_int8_t shortPreamble; /* mask for enabling short * preamble in CCK rate code */ @@ -501,6 +522,46 @@ } HAL_RATE_SET; /* + * 802.11n specific structures and enums + */ +typedef enum { + HAL_CHAINTYPE_TX = 1, /* Tx chain type */ + HAL_CHAINTYPE_RX = 2, /* RX chain type */ +} HAL_CHAIN_TYPE; + +typedef struct { + u_int Tries; + u_int Rate; + u_int PktDuration; + u_int ChSel; + u_int RateFlags; +#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ +#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ +#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ +} HAL_11N_RATE_SERIES; + +typedef enum { + HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ + HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ +} HAL_HT_MACMODE; + +typedef enum { + HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ + HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ +} HAL_HT_PHYMODE; + +typedef enum { + HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ + HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ +} HAL_HT_EXTPROTSPACING; + + +typedef enum { + HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ + HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ +} HAL_HT_RXCLEAR; + +/* * Antenna switch control. By default antenna selection * enables multiple (2) antenna use. To force use of the * A or B antenna only specify a fixed setting. Fixing @@ -525,6 +586,7 @@ u_int16_t kv_len; /* length in bits */ u_int8_t kv_val[16]; /* enough for 128-bit keys */ u_int8_t kv_mic[8]; /* TKIP MIC key */ + u_int8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ } HAL_KEYVAL; typedef enum { @@ -569,7 +631,7 @@ /* * Like HAL_BEACON_STATE but for non-station mode setup. - * NB: see above flag definitions + * NB: see above flag definitions for bt_intval. */ typedef struct { u_int32_t bt_intval; /* beacon interval+flags */ @@ -577,6 +639,10 @@ u_int32_t bt_nextatim; /* next ATIM in TU */ u_int32_t bt_nextdba; /* next DBA in 1/8th TU */ u_int32_t bt_nextswba; /* next SWBA in 1/8th TU */ + u_int32_t bt_flags; /* timer enables */ +#define HAL_BEACON_TBTT_EN 0x00000001 +#define HAL_BEACON_DBA_EN 0x00000002 +#define HAL_BEACON_SWBA_EN 0x00000004 } HAL_BEACON_TIMERS; /* @@ -592,6 +658,8 @@ #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ struct ath_desc; +struct ath_tx_status; +struct ath_rx_status; /* * Hardware Access Layer (HAL) API. @@ -606,7 +674,7 @@ struct ath_hal { u_int32_t ah_magic; /* consistency check magic number */ u_int32_t ah_abi; /* HAL ABI version */ -#define HAL_ABI_VERSION 0x06052200 /* YYMMDDnn */ +#define HAL_ABI_VERSION 0x07090300 /* YYMMDDnn */ u_int16_t ah_devid; /* PCI device ID */ u_int16_t ah_subvendorid; /* PCI subvendor ID */ HAL_SOFTC ah_sc; /* back pointer to driver/os state */ @@ -620,7 +688,7 @@ /* NB: when only one radio is present the rev is in 5Ghz */ u_int16_t ah_analog5GhzRev;/* 5GHz radio revision */ u_int16_t ah_analog2GhzRev;/* 2GHz radio revision */ - u_int8_t ah_decompMask[HAL_DECOMP_MASK_SIZE]; /* decomp mask array */ + const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, u_int mode); void __ahdecl(*ah_detach)(struct ath_hal*); @@ -635,12 +703,7 @@ HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *, HAL_BOOL *); HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, u_int32_t); - void __ahdecl(*ah_arEnable)(struct ath_hal *); - void __ahdecl(*ah_arDisable)(struct ath_hal *); - void __ahdecl(*ah_arReset)(struct ath_hal *); - HAL_BOOL __ahdecl(*ah_radarHaveEvent)(struct ath_hal *); - HAL_BOOL __ahdecl(*ah_processDfs)(struct ath_hal *, HAL_CHANNEL *); - u_int32_t __ahdecl(*ah_dfsNolCheck)(struct ath_hal *, HAL_CHANNEL *, u_int32_t); + /* DFS support */ HAL_BOOL __ahdecl(*ah_radarWait)(struct ath_hal *, HAL_CHANNEL *); /* Transmit functions */ @@ -674,7 +737,8 @@ HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, const struct ath_desc *); - HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, struct ath_desc*); + HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, + struct ath_desc *, struct ath_tx_status *); void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, u_int32_t *); void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); @@ -695,9 +759,10 @@ void __ahdecl(*ah_setRxFilter)(struct ath_hal*, u_int32_t); HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, u_int32_t size, u_int flags); - HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, struct ath_desc *, - u_int32_t phyAddr, struct ath_desc *next, - u_int64_t tsf); + HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, + struct ath_desc *, u_int32_t phyAddr, + struct ath_desc *next, u_int64_t tsf, + struct ath_rx_status *); void __ahdecl(*ah_rxMonitor)(struct ath_hal *, const HAL_NODE_STATS *, HAL_CHANNEL *); void __ahdecl(*ah_procMibEvent)(struct ath_hal *, @@ -768,7 +833,6 @@ HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, HAL_CHANNEL *); - /* Beacon Management Functions */ void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, const HAL_BEACON_TIMERS *); @@ -812,9 +876,7 @@ /* * Set the Vendor ID for Vendor SKU's which can modify the * channel properties returned by ath_hal_init_channels. - * Return AH_TRUE if set succeeds */ - extern HAL_BOOL __ahdecl ath_hal_setvendor(struct ath_hal *, u_int32_t ); /* @@ -831,7 +893,7 @@ extern HAL_BOOL __ahdecl ath_hal_init_channels(struct ath_hal *, HAL_CHANNEL *chans, u_int maxchans, u_int *nchans, u_int8_t *regclassids, u_int maxregids, u_int *nregids, - HAL_CTRY_CODE cc, u_int16_t modeSelect, + HAL_CTRY_CODE cc, u_int modeSelect, HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels); /* @@ -846,12 +908,6 @@ extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*, HAL_CTRY_CODE); /* - * Return rate table for specified mode (11a, 11b, 11g, etc). - */ -extern const HAL_RATE_TABLE * __ahdecl ath_hal_getratetable(struct ath_hal *, - u_int mode); - -/* * Calculate the transmit duration of a frame. */ extern u_int16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, @@ -864,6 +920,11 @@ extern HAL_BOOL __ahdecl ath_hal_ispublicsafetysku(struct ath_hal *); /* + * Return if device is operating in 900 MHz band. + */ +extern HAL_BOOL ath_hal_isgsmsku(struct ath_hal *); + +/* * Convert between IEEE channel number and channel frequency * using the specified channel flags; e.g. CHANNEL_2GHZ. */ Index: sys/contrib/dev/ath/ah_desc.h =================================================================== RCS file: /cvsroot/src/sys/contrib/dev/ath/ah_desc.h,v retrieving revision 1.2 diff -u -r1.2 ah_desc.h --- sys/contrib/dev/ath/ah_desc.h 5 Jun 2006 05:14:38 -0000 1.2 +++ sys/contrib/dev/ath/ah_desc.h 2 Jun 2008 00:18:47 -0000 @@ -86,15 +86,27 @@ * -96dBm absolute power in a 20MHz channel. */ struct ath_rx_status { - u_int16_t rs_datalen; /* rx frame length */ - u_int16_t rs_tstamp; /* h/w assigned timestamp */ - u_int8_t rs_status; /* rx status, 0 => recv ok */ - u_int8_t rs_phyerr; /* phy error code */ - int8_t rs_rssi; /* rx frame RSSI */ - u_int8_t rs_keyix; /* key cache index */ - u_int8_t rs_rate; /* h/w receive rate index */ - u_int8_t rs_antenna; /* antenna information */ - u_int8_t rs_more; /* more descriptors follow */ + u_int16_t rs_datalen; /* rx frame length */ + u_int8_t rs_status; /* rx status, 0 => recv ok */ + u_int8_t rs_phyerr; /* phy error code */ + int8_t rs_rssi; /* rx frame RSSI (combined for 11n) */ + u_int8_t rs_keyix; /* key cache index */ + u_int8_t rs_rate; /* h/w receive rate index */ + u_int8_t rs_more; /* more descriptors follow */ + u_int32_t rs_tstamp; /* h/w assigned timestamp */ + u_int32_t rs_antenna; /* antenna information */ +#ifdef AH_SUPPORT_AR5416 + /* 802.11n status */ + int8_t rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */ + int8_t rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */ + u_int8_t rs_isaggr; /* is part of the aggregate */ + u_int8_t rs_moreaggr; /* more frames in aggr to follow */ + u_int8_t rs_num_delims; /* number of delims in aggr */ + u_int8_t rs_flags; /* misc flags */ + u_int32_t rs_evm0; /* evm bytes */ + u_int32_t rs_evm1; + u_int32_t rs_evm2; +#endif /* AH_SUPPORT_AR5416 */ }; #define HAL_RXERR_CRC 0x01 /* CRC error on frame */ Index: sys/contrib/dev/ath/version.h =================================================================== RCS file: /cvsroot/src/sys/contrib/dev/ath/version.h,v retrieving revision 1.2 diff -u -r1.2 version.h --- sys/contrib/dev/ath/version.h 5 Jun 2006 05:14:38 -0000 1.2 +++ sys/contrib/dev/ath/version.h 2 Jun 2008 00:18:47 -0000 @@ -33,6 +33,6 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * - * $Id: version.h,v 1.2 2006/06/05 05:14:38 gdamore Exp $ + * $Id: //depot/sw/branches/linux_hal/version.h#5 $ */ -#define ATH_HAL_VERSION "0.9.17.2" +#define ATH_HAL_VERSION "0.10.2.2-ATHEROS" Index: sys/contrib/dev/ath/public/i386-elf.hal.o.uu =================================================================== RCS file: /cvsroot/src/sys/contrib/dev/ath/public/i386-elf.hal.o.uu,v retrieving revision 1.2 diff -u -r1.2 i386-elf.hal.o.uu --- sys/contrib/dev/ath/public/i386-elf.hal.o.uu 5 Jun 2006 05:14:39 -0000 1.2 +++ sys/contrib/dev/ath/public/i386-elf.hal.o.uu 2 Jun 2008 00:18:52 -0000 @@ -33,2535 +33,3823 @@ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGES. * - * $Id: i386-elf.hal.o.uu,v 1.2 2006/06/05 05:14:39 gdamore Exp $ + * $Id: //depot/sw/branches/linux_hal/COPYRIGHT#1 $ */ -#define ATH_HAL_VERSION "0.9.17.2" +#define ATH_HAL_VERSION "0.10.2.2-ATHEROS" begin 644 hal.o -M?T5,1@$!`0D```````````$``P`!``````````````!#^!$/C;\```"#^`M4 -M/100``!T5.M:B?8]$Q$``'1)/1,1``!_"3T2$0``=";K0;ID````/1/P``!T -M/;IX````/1OQ``!T,>LGC78`NHP```#K);J9````ZQZZI@```.L7NKD```#K -M$+K,````ZPF0N@````"-=@")T,.0BU0D!(M$)`AF@?J,%G039H'Z)Z=T#+D` -M````9H'ZMQ!U#@^WP%#HN?[__X/$!(G!B#^!$/C8X```"#^`?````ZU&0/1,1``!T3CT3$0``?R(] -M!Q$``'1O/0<1``!_"3T4$```="WK=ST2$0``=$#K;HGV/1OQ``!T-3T;\0`` -M?PD]$_```'00ZU4]&?\``'5.B?:Z$P```(/L#%%35EXN&S!```&:#>`(`>2N)VL'B!+C336(0 -M]^+!Z@:-3/H5BH&C4SZ%8G(B=.Z`````/?SC02% -M)````.MLC13=`````+C336(0]^+!Z@:-3/H5B@"Z?\```"-DWCL__^XS@$@\`/ZQ60C9-X[/__N,W,S,SWXHG0 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