Index: pci/pciidevar.h =================================================================== RCS file: /cvsroot/src/sys/dev/pci/pciidevar.h,v retrieving revision 1.36 diff -u -r1.36 pciidevar.h --- pci/pciidevar.h 4 Jan 2008 00:27:27 -0000 1.36 +++ pci/pciidevar.h 18 Aug 2008 13:14:12 -0000 @@ -39,6 +39,7 @@ * Author: Christopher G. Demetriou, March 2, 1998. */ +#include #include #include #include @@ -78,6 +79,12 @@ struct wdc_softc sc_wdcdev; /* common wdc definitions */ pci_chipset_tag_t sc_pc; /* PCI registers info */ pcitag_t sc_tag; + cardbus_devfunc_t sc_ct; /* Cardbus registers info */ + cardbus_chipset_tag_t sc_cc; + cardbus_function_tag_t sc_cf; + cardbustag_t sc_ctag; + bus_size_t sc_cmdsize[PCIIDE_NUM_CHANNELS]; + bus_size_t sc_ctlsize[PCIIDE_NUM_CHANNELS]; void *sc_pci_ih; /* PCI interrupt handle */ #if NATA_DMA int sc_dma_ok; /* bus-master DMA info */ @@ -90,6 +97,7 @@ */ bus_space_tag_t sc_dma_iot; bus_space_handle_t sc_dma_ioh; + bus_size_t sc_dma_size; bus_dma_tag_t sc_dmat; /* @@ -165,6 +176,8 @@ const char *ide_name; /* map and setup chip, probe drives */ void (*chip_map)(struct pciide_softc*, struct pci_attach_args*); + void (*cardbus_chip_map)(struct pciide_softc*, + struct cardbus_attach_args*); }; /* Flags for ide_flags */ Index: cardbus/cardbusvar.h =================================================================== RCS file: /cvsroot/src/sys/dev/cardbus/cardbusvar.h,v retrieving revision 1.43 diff -u -r1.43 cardbusvar.h --- cardbus/cardbusvar.h 26 Jun 2008 12:33:17 -0000 1.43 +++ cardbus/cardbusvar.h 18 Aug 2008 13:13:55 -0000 @@ -35,8 +35,10 @@ #ifndef _DEV_CARDBUS_CARDBUSVAR_H_ #define _DEV_CARDBUS_CARDBUSVAR_H_ +#include "cardbus.h" + #include -#if 1 +#if NCARDBUS > 0 #include #endif Index: cardbus/files.cardbus =================================================================== RCS file: /cvsroot/src/sys/dev/cardbus/files.cardbus,v retrieving revision 1.34 diff -u -r1.34 files.cardbus --- cardbus/files.cardbus 7 Sep 2006 14:22:07 -0000 1.34 +++ cardbus/files.cardbus 18 Aug 2008 13:13:55 -0000 @@ -131,3 +131,9 @@ # attach njata at cardbus with njata_cardbus file dev/cardbus/njata_cardbus.c njata_cardbus + +# +# PCI IDE controllers +# +define pciide_cardbus_common +file dev/cardbus/pciide_cardbus_common.c pciide_cardbus_common Index: pci/acardide.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/acardide.c,v retrieving revision 1.23 diff -u -r1.23 acardide.c --- pci/acardide.c 14 May 2008 13:29:29 -0000 1.23 +++ pci/acardide.c 18 Aug 2008 13:13:57 -0000 @@ -53,31 +53,37 @@ 0, "Acard ATP850U Ultra33 IDE Controller", acard_chip_map, + NULL, }, { PCI_PRODUCT_ACARD_ATP860, 0, "Acard ATP860 Ultra66 IDE Controller", acard_chip_map, + NULL, }, { PCI_PRODUCT_ACARD_ATP860A, 0, "Acard ATP860-A Ultra66 IDE Controller", acard_chip_map, + NULL, }, { PCI_PRODUCT_ACARD_ATP865, 0, "Acard ATP865 Ultra133 IDE Controller", acard_chip_map, + NULL, }, { PCI_PRODUCT_ACARD_ATP865A, 0, "Acard ATP865-A Ultra133 IDE Controller", acard_chip_map, + NULL, }, { 0, 0, NULL, - NULL + NULL, + NULL, } }; Index: pci/aceride.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/aceride.c,v retrieving revision 1.25 diff -u -r1.25 aceride.c --- pci/aceride.c 18 Mar 2008 20:46:36 -0000 1.25 +++ pci/aceride.c 18 Aug 2008 13:13:57 -0000 @@ -63,10 +63,12 @@ 0, "Acer Labs M5229 UDMA IDE Controller", acer_chip_map, + NULL, }, { 0, 0, NULL, + NULL, NULL } }; Index: pci/artsata.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/artsata.c,v retrieving revision 1.18 diff -u -r1.18 artsata.c --- pci/artsata.c 28 Apr 2008 20:23:54 -0000 1.18 +++ pci/artsata.c 18 Aug 2008 13:13:57 -0000 @@ -59,10 +59,12 @@ 0, "Intel 31244 Serial ATA Controller", artisea_chip_map, + NULL, }, { 0, 0, NULL, + NULL, NULL } }; Index: pci/cmdide.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/cmdide.c,v retrieving revision 1.28 diff -u -r1.28 cmdide.c --- pci/cmdide.c 18 Mar 2008 20:46:36 -0000 1.28 +++ pci/cmdide.c 18 Aug 2008 13:13:58 -0000 @@ -65,36 +65,43 @@ { PCI_PRODUCT_CMDTECH_640, 0, "CMD Technology PCI0640", - cmd_chip_map + cmd_chip_map, + NULL, }, { PCI_PRODUCT_CMDTECH_643, 0, "CMD Technology PCI0643", cmd0643_9_chip_map, + NULL, }, { PCI_PRODUCT_CMDTECH_646, 0, "CMD Technology PCI0646", cmd0643_9_chip_map, + NULL, }, { PCI_PRODUCT_CMDTECH_648, 0, "CMD Technology PCI0648", cmd0643_9_chip_map, + NULL, }, { PCI_PRODUCT_CMDTECH_649, 0, "CMD Technology PCI0649", cmd0643_9_chip_map, + NULL, }, { PCI_PRODUCT_CMDTECH_680, 0, "Silicon Image 0680", cmd680_chip_map, + NULL, }, { 0, 0, NULL, + NULL, NULL } }; Index: pci/cypide.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/cypide.c,v retrieving revision 1.21 diff -u -r1.21 cypide.c --- pci/cypide.c 18 Mar 2008 20:46:36 -0000 1.21 +++ pci/cypide.c 18 Aug 2008 13:13:58 -0000 @@ -58,10 +58,12 @@ IDE_16BIT_IOSPACE, "Cypress 82C693 IDE Controller", cy693_chip_map, + NULL, }, { 0, 0, NULL, + NULL, NULL } }; Index: pci/geodeide.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/geodeide.c,v retrieving revision 1.15 diff -u -r1.15 geodeide.c --- pci/geodeide.c 18 Mar 2008 20:46:36 -0000 1.15 +++ pci/geodeide.c 18 Aug 2008 13:13:59 -0000 @@ -67,16 +67,19 @@ 0, "AMD Geode CX5530 IDE controller", geodeide_chip_map, + NULL, }, { PCI_PRODUCT_NS_SC1100_IDE, 0, "AMD Geode SC1100 IDE controller", geodeide_chip_map, + NULL, }, { 0, 0, NULL, NULL, + NULL, }, }; Index: pci/hptide.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/hptide.c,v retrieving revision 1.25 diff -u -r1.25 hptide.c --- pci/hptide.c 18 Mar 2008 20:46:36 -0000 1.25 +++ pci/hptide.c 18 Aug 2008 13:13:59 -0000 @@ -55,31 +55,37 @@ { PCI_PRODUCT_TRIONES_HPT302, 0, NULL, - hpt_chip_map + hpt_chip_map, + NULL, }, { PCI_PRODUCT_TRIONES_HPT366, 0, NULL, hpt_chip_map, + NULL, }, { PCI_PRODUCT_TRIONES_HPT371, 0, NULL, hpt_chip_map, + NULL, }, { PCI_PRODUCT_TRIONES_HPT372A, 0, NULL, - hpt_chip_map + hpt_chip_map, + NULL, }, { PCI_PRODUCT_TRIONES_HPT374, 0, NULL, - hpt_chip_map + hpt_chip_map, + NULL, }, { 0, 0, NULL, + NULL, NULL } }; Index: pci/optiide.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/optiide.c,v retrieving revision 1.17 diff -u -r1.17 optiide.c --- pci/optiide.c 28 Apr 2008 20:23:55 -0000 1.17 +++ pci/optiide.c 18 Aug 2008 13:13:59 -0000 @@ -55,20 +55,24 @@ 0, "OPTi 82c621 PCI IDE controller", opti_chip_map, + NULL, }, { PCI_PRODUCT_OPTI_82C568, 0, "OPTi 82c568 (82c621 compatible) PCI IDE controller", opti_chip_map, + NULL, }, { PCI_PRODUCT_OPTI_82D568, 0, "OPTi 82d568 (82c621 compatible) PCI IDE controller", opti_chip_map, + NULL, }, { 0, 0, NULL, + NULL, NULL } }; Index: pci/pciide_common.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/pciide_common.c,v retrieving revision 1.38 diff -u -r1.38 pciide_common.c --- pci/pciide_common.c 18 Mar 2008 20:46:37 -0000 1.38 +++ pci/pciide_common.c 18 Aug 2008 13:14:12 -0000 @@ -106,6 +106,7 @@ 0, "Generic PCI IDE controller", default_chip_map, + NULL, }; const struct pciide_product_desc * @@ -113,11 +114,11 @@ pcireg_t id; const struct pciide_product_desc *pp; { - for (; pp->chip_map != NULL; pp++) + for (; pp->chip_map != NULL || pp->cardbus_chip_map != NULL; pp++) if (PCI_PRODUCT(id) == pp->ide_product) break; - if (pp->chip_map == NULL) + if (pp->chip_map == NULL && pp->cardbus_chip_map == NULL) return NULL; return pp; } Index: pci/pdcide.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/pdcide.c,v retrieving revision 1.26 diff -u -r1.26 pdcide.c --- pci/pdcide.c 18 Mar 2008 20:46:37 -0000 1.26 +++ pci/pdcide.c 18 Aug 2008 13:14:12 -0000 @@ -60,60 +60,72 @@ 0, "Promise Ultra33/ATA Bus Master IDE Accelerator", pdc202xx_chip_map, + NULL, }, { PCI_PRODUCT_PROMISE_PDC20262, 0, "Promise Ultra66/ATA Bus Master IDE Accelerator", pdc202xx_chip_map, + NULL, }, { PCI_PRODUCT_PROMISE_PDC20267, 0, "Promise Ultra100/ATA Bus Master IDE Accelerator", pdc202xx_chip_map, + NULL, }, { PCI_PRODUCT_PROMISE_PDC20265, 0, "Promise Ultra100/ATA Bus Master IDE Accelerator", pdc202xx_chip_map, + NULL, }, { PCI_PRODUCT_PROMISE_PDC20268, 0, "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", pdc202xx_chip_map, + NULL, }, { PCI_PRODUCT_PROMISE_PDC20270, 0, "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", pdc202xx_chip_map, + NULL, }, { PCI_PRODUCT_PROMISE_PDC20269, 0, "Promise Ultra133/ATA Bus Master IDE Accelerator", pdc202xx_chip_map, + NULL, }, { PCI_PRODUCT_PROMISE_PDC20276, 0, "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", pdc202xx_chip_map, + NULL, }, { PCI_PRODUCT_PROMISE_PDC20275, 0, "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", pdc202xx_chip_map, + NULL, }, { PCI_PRODUCT_PROMISE_PDC20271, 0, "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", pdc202xx_chip_map, + NULL, }, { PCI_PRODUCT_PROMISE_PDC20277, 0, "Promise Fasttrak133 Lite Bus Master IDE Accelerator", pdc202xx_chip_map, + NULL, }, { 0, 0, NULL, + NULL, NULL } }; Index: pci/piixide.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/piixide.c,v retrieving revision 1.46 diff -u -r1.46 piixide.c --- pci/piixide.c 18 Mar 2008 20:46:37 -0000 1.46 +++ pci/piixide.c 18 Aug 2008 13:14:12 -0000 @@ -60,195 +60,234 @@ 0, "Intel 82092AA IDE controller", default_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82371FB_IDE, 0, "Intel 82371FB IDE controller (PIIX)", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82371SB_IDE, 0, "Intel 82371SB IDE Interface (PIIX3)", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82371AB_IDE, 0, "Intel 82371AB IDE controller (PIIX4)", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82440MX_IDE, 0, "Intel 82440MX IDE controller", - piix_chip_map + piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801AA_IDE, 0, "Intel 82801AA IDE Controller (ICH)", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801AB_IDE, 0, "Intel 82801AB IDE Controller (ICH0)", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801BA_IDE, 0, "Intel 82801BA IDE Controller (ICH2)", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801BAM_IDE, 0, "Intel 82801BAM IDE Controller (ICH2-M)", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801CA_IDE_1, 0, "Intel 82801CA IDE Controller (ICH3)", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801CA_IDE_2, 0, "Intel 82801CA IDE Controller (ICH3)", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801DB_IDE, 0, "Intel 82801DB IDE Controller (ICH4)", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801DBM_IDE, 0, "Intel 82801DBM IDE Controller (ICH4-M)", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801EB_IDE, 0, "Intel 82801EB IDE Controller (ICH5)", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801EB_SATA, 0, "Intel 82801EB Serial ATA Controller", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801ER_SATA, 0, "Intel 82801ER Serial ATA/Raid Controller", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_6300ESB_IDE, 0, "Intel 6300ESB IDE Controller (ICH5)", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_6300ESB_SATA, 0, "Intel 6300ESB Serial ATA Controller", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_6300ESB_RAID, 0, "Intel 6300ESB Serial ATA/RAID Controller", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801FB_IDE, 0, "Intel 82801FB IDE Controller (ICH6)", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801FB_SATA, 0, "Intel 82801FB Serial ATA/Raid Controller", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801FR_SATA, 0, "Intel 82801FR Serial ATA/Raid Controller", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801FBM_SATA, 0, "Intel 82801FBM Serial ATA Controller (ICH6)", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801G_IDE, 0, "Intel 82801GB/GR IDE Controller (ICH7)", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801G_SATA, 0, "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801GBM_SATA, 0, "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801H_SATA_1, 0, "Intel 82801H Serial ATA Controller (ICH8)", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 0, "Intel 82801H Serial ATA RAID Controller (ICH8)", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801H_SATA_2, 0, "Intel 82801H Serial ATA Controller (ICH8)", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801HBM_IDE, 0, "Intel 82801HBM IDE Controller (ICH8M)", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 0, "Intel 82801HBM Serial ATA Controller (ICH8M)", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 0, "Intel 82801HBM Serial ATA Controller (ICH8M)", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801HEM_SATA, 0, "Intel 82801HEM Serial ATA Controller (ICH8M)", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_63XXESB_IDE, 0, "Intel 631xESB/632xESB IDE Controller", piix_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801I_SATA_1, 0, "Intel 82801I Serial ATA Controller (ICH9)", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801I_SATA_2, 0, "Intel 82801I Serial ATA Controller (ICH9)", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_82801I_SATA_3, 0, "Intel 82801I Serial ATA Controller (ICH9)", piixsata_chip_map, + NULL, }, { PCI_PRODUCT_INTEL_63XXESB_SATA, 0, "Intel 631xESB/632xESB Serial ATA Controller", piixsata_chip_map, + NULL, }, { 0, 0, NULL, + NULL, NULL } }; Index: pci/satalink.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/satalink.c,v retrieving revision 1.38 diff -u -r1.38 satalink.c --- pci/satalink.c 28 Apr 2008 20:23:55 -0000 1.38 +++ pci/satalink.c 18 Aug 2008 13:14:13 -0000 @@ -272,21 +232,25 @@ 0, "Silicon Image SATALink 3112", sii3112_chip_map, + NULL, }, { PCI_PRODUCT_CMDTECH_3512, 0, "Silicon Image SATALink 3512", sii3112_chip_map, + NULL, }, { PCI_PRODUCT_CMDTECH_AAR_1210SA, 0, "Adaptec AAR-1210SA serial ATA RAID controller", sii3112_chip_map, + NULL, }, { PCI_PRODUCT_CMDTECH_3114, 0, "Silicon Image SATALink 3114", sii3114_chip_map, + NULL, }, { 0, 0, Index: pci/siside.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/siside.c,v retrieving revision 1.23 diff -u -r1.23 siside.c --- pci/siside.c 18 Mar 2008 20:46:37 -0000 1.23 +++ pci/siside.c 18 Aug 2008 13:14:13 -0000 @@ -60,25 +60,30 @@ 0, NULL, sis_chip_map, + NULL, }, { PCI_PRODUCT_SIS_180_SATA, 0, NULL, sis_sata_chip_map, + NULL, }, { PCI_PRODUCT_SIS_181_SATA, 0, NULL, sis_sata_chip_map, + NULL, }, { PCI_PRODUCT_SIS_182_SATA, 0, NULL, sis_sata_chip_map, + NULL, }, { 0, 0, NULL, + NULL, NULL } }; Index: pci/slide.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/slide.c,v retrieving revision 1.20 diff -u -r1.20 slide.c --- pci/slide.c 28 Apr 2008 20:23:55 -0000 1.20 +++ pci/slide.c 18 Aug 2008 13:14:13 -0000 @@ -55,11 +55,13 @@ 0, "Symphony Labs 82C105 IDE controller", sl82c105_chip_map, + NULL, }, { 0, 0, NULL, NULL, + NULL, } }; @@ -68,11 +70,13 @@ 0, "Winbond W83C553F IDE controller", sl82c105_chip_map, + NULL, }, { 0, 0, NULL, NULL, + NULL, } }; Index: pci/viaide.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/viaide.c,v retrieving revision 1.56 diff -u -r1.56 viaide.c --- pci/viaide.c 17 Jun 2008 17:03:14 -0000 1.56 +++ pci/viaide.c 18 Aug 2008 13:14:13 -0000 @@ -76,31 +76,37 @@ { PCI_PRODUCT_AMD_PBC756_IDE, 0, "Advanced Micro Devices AMD756 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_AMD_PBC766_IDE, 0, "Advanced Micro Devices AMD766 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_AMD_PBC768_IDE, 0, "Advanced Micro Devices AMD768 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_AMD_PBC8111_IDE, 0, "Advanced Micro Devices AMD8111 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_AMD_CS5536_IDE, 0, "Advanced Micro Devices CS5536 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { 0, 0, NULL, + NULL, NULL } }; @@ -109,186 +115,223 @@ { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 0, "NVIDIA nForce IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 0, "NVIDIA nForce2 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 0, "NVIDIA nForce2 Ultra 400 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 0, "NVIDIA nForce2 Ultra 400 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 0, "NVIDIA nForce3 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 0, "NVIDIA nForce3 250 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 0, "NVIDIA nForce3 250 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 0, "NVIDIA nForce3 250 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 0, "NVIDIA nForce4 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 0, "NVIDIA nForce4 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 0, "NVIDIA nForce4 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 0, "NVIDIA nForce430 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 0, "NVIDIA nForce430 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 0, "NVIDIA nForce430 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP04_IDE, 0, "NVIDIA MCP04 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP04_SATA, 0, "NVIDIA MCP04 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 0, "NVIDIA MCP04 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP55_IDE, 0, "NVIDIA MCP55 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP55_SATA, 0, "NVIDIA MCP55 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 0, "NVIDIA MCP55 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP61_IDE, 0, "NVIDIA MCP61 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP65_IDE, 0, "NVIDIA MCP65 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP73_IDE, 0, "NVIDIA MCP73 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP77_IDE, 0, "NVIDIA MCP77 IDE Controller", - via_chip_map + via_chip_map, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP61_SATA, 0, "NVIDIA MCP61 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 0, "NVIDIA MCP61 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 0, "NVIDIA MCP61 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP65_SATA, 0, "NVIDIA MCP65 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 0, "NVIDIA MCP65 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 0, "NVIDIA MCP65 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 0, "NVIDIA MCP65 Serial ATA Controller", - via_sata_chip_map_6 + via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP67_IDE, 0, "NVIDIA MCP67 IDE Controller", via_chip_map, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP67_SATA, 0, "NVIDIA MCP67 Serial ATA Controller", via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 0, "NVIDIA MCP67 Serial ATA Controller", via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 0, "NVIDIA MCP67 Serial ATA Controller", via_sata_chip_map_6, + NULL, }, { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 0, "NVIDIA MCP67 Serial ATA Controller", via_sata_chip_map_6, + NULL, }, { 0, 0, NULL, + NULL, NULL } }; @@ -298,40 +341,48 @@ 0, NULL, via_chip_map, + NULL, }, { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 0, NULL, via_chip_map, + NULL, }, { PCI_PRODUCT_VIATECH_CX700_IDE, 0, NULL, via_chip_map, + NULL, }, { PCI_PRODUCT_VIATECH_VT6421_RAID, 0, "VIA Technologies VT6421 Serial RAID Controller", via_sata_chip_map_new, + NULL, }, { PCI_PRODUCT_VIATECH_VT8237_SATA, 0, "VIA Technologies VT8237 SATA Controller", via_sata_chip_map_7, + NULL, }, { PCI_PRODUCT_VIATECH_VT8237A_SATA, 0, "VIA Technologies VT8237A SATA Controller", via_sata_chip_map_7, + NULL, }, { PCI_PRODUCT_VIATECH_VT8237R_SATA, 0, "VIA Technologies VT8237R SATA Controller", via_sata_chip_map_0, + NULL, }, { 0, 0, NULL, + NULL, NULL } }; --- cardbus/pciide_cardbus_common.c.orig 1970-01-01 09:00:00.000000000 +0900 +++ cardbus/pciide_cardbus_common.c 2008-08-17 23:05:26.000000000 +0900 @@ -0,0 +1,394 @@ +/* $NetBSD: pciide_common.c,v 1.38 2008/03/18 20:46:37 cube Exp $ */ + + +/* + * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Manuel Bouyer. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +/* + * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Christopher G. Demetriou + * for the NetBSD Project. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * PCI IDE controller driver. + * + * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD + * sys/dev/pci/ppb.c, revision 1.16). + * + * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and + * "Programming Interface for Bus Master IDE Controller, Revision 1.0 + * 5/16/94" from the PCI SIG. + * + */ + +#include +__KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.38 2008/03/18 20:46:37 cube Exp $"); + +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include + +#ifdef ATADEBUG +extern int atadebug_pciide_mask; +#endif + +#if NATA_DMA +static const char dmaerrfmt[] = + "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; +#endif + + +void +pciide_cardbus_common_attach(struct pciide_softc *sc, + struct cardbus_attach_args *ca, + const struct pciide_product_desc *pp) +{ + cardbus_devfunc_t ct = ca->ca_ct; + cardbus_chipset_tag_t cc = ct->ct_cc; + cardbus_function_tag_t cf = ct->ct_cf; + cardbustag_t tag = ca->ca_tag; +#if NATA_DMA + cardbusreg_t csr; +#endif + const char *displaydev; + + aprint_naive(": disk controller\n"); + aprint_normal("\n"); + + sc->sc_pci_id = ca->ca_id; + sc->sc_pp = pp; + displaydev = sc->sc_pp->ide_name; + + aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, "%s (rev. 0x%02x)\n", + displaydev, CARDBUS_REVISION(ca->ca_class)); + + sc->sc_ct = ct; + sc->sc_cc = cc; + sc->sc_cf = cf; + sc->sc_ctag = ca->ca_tag; + + (cf->cardbus_ctrl)(cc, CARDBUS_IO_ENABLE); + (cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE); + (cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); + +#if NATA_DMA + /* Set up DMA defaults; these might be adjusted by chip_map. */ + sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; + sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; +#endif + +#if 0 +#ifdef ATADEBUG + if (atadebug_pciide_mask & DEBUG_PROBE) + pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); +#endif +#endif + sc->sc_pp->cardbus_chip_map(sc, ca); + + csr = cardbus_conf_read(cc, cf, tag, CARDBUS_COMMAND_STATUS_REG); + csr |= (PCI_COMMAND_IO_ENABLE | CARDBUS_COMMAND_MEM_ENABLE); +#if NATA_DMA + if (sc->sc_dma_ok) + csr |= PCI_COMMAND_MASTER_ENABLE; +#endif + cardbus_conf_write(cc, cf, tag, CARDBUS_COMMAND_STATUS_REG, csr); + + ATADEBUG_PRINT(("pciide: command/status register=%x\n", + cardbus_conf_read(cc, cf, tag, CARDBUS_COMMAND_STATUS_REG)), + DEBUG_PROBE); +} + +int +pciide_cardbus_common_detach(struct pciide_softc *sc, int force) +{ + struct pciide_channel *cp; + struct ata_channel *wdc_cp; + struct wdc_regs *wdr; + int chan, rv; + + rv = wdcdetach(sc->sc_wdcdev.sc_atac.atac_dev, force); + + if (sc->sc_pci_ih != NULL) + cardbus_intr_disestablish(sc->sc_cc, sc->sc_cf, sc->sc_pci_ih); + if (sc->sc_dma_ok) + Cardbus_mapreg_unmap(sc->sc_ct, PCIIDE_REG_BUS_MASTER_DMA, + sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_size); + for (chan = 0; chan < sc->sc_wdcdev.sc_atac.atac_nchannels; chan++) { + cp = &sc->pciide_channels[chan]; + wdc_cp = &cp->ata_channel; + wdr = CHAN_TO_WDC_REGS(wdc_cp); + if (sc->sc_cmdsize[chan]) + Cardbus_mapreg_unmap(sc->sc_ct, + PCIIDE_REG_CMD_BASE(chan), wdr->cmd_iot, + wdr->cmd_baseioh, sc->sc_cmdsize[chan]); + if (sc->sc_ctlsize[chan]) + Cardbus_mapreg_unmap(sc->sc_ct, + PCIIDE_REG_CTL_BASE(chan), wdr->ctl_iot, + cp->ctl_baseioh, sc->sc_ctlsize[chan]); + } + return rv; +} + +void +pciide_cardbus_mapregs_native(struct cardbus_attach_args *ca, + struct pciide_channel *cp, + int (*pci_intr)(void *)) +{ + struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); + cardbus_devfunc_t ct = ca->ca_ct; + cardbus_chipset_tag_t cc = ct->ct_cc; + cardbus_function_tag_t cf = ct->ct_cf; + struct ata_channel *wdc_cp = &cp->ata_channel; + struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); + int i; + + cp->compat = 0; + + if (sc->sc_pci_ih == NULL) { + sc->sc_pci_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, + IPL_BIO, pci_intr, sc); + if (sc->sc_pci_ih == NULL) { + aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, + "couldn't establish interrupt\n"); + goto bad; + } + } + cp->ih = sc->sc_pci_ih; + if (Cardbus_mapreg_map(ct, PCIIDE_REG_CMD_BASE(wdc_cp->ch_channel), + CARDBUS_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, + NULL, &sc->sc_cmdsize[wdc_cp->ch_channel]) != 0) { + aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, + "couldn't map %s channel cmd regs\n", cp->name); + goto bad; + } + + if (Cardbus_mapreg_map(ct, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel), + CARDBUS_MAPREG_TYPE_IO, 0, &wdr->ctl_iot, &cp->ctl_baseioh, + NULL, &sc->sc_ctlsize[wdc_cp->ch_channel]) != 0) { + aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, + "couldn't map %s channel ctl regs\n", cp->name); + bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, + sc->sc_cmdsize[wdc_cp->ch_channel]); + goto bad; + } + /* + * In native mode, 4 bytes of I/O space are mapped for the control + * register, the control register is at offset 2. Pass the generic + * code a handle for only one byte at the right offset. + */ + if (bus_space_subregion(wdr->ctl_iot, cp->ctl_baseioh, 2, 1, + &wdr->ctl_ioh) != 0) { + aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, + "unable to subregion %s channel ctl regs\n", cp->name); + bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, + sc->sc_cmdsize[wdc_cp->ch_channel]); + bus_space_unmap(wdr->cmd_iot, cp->ctl_baseioh, + sc->sc_ctlsize[wdc_cp->ch_channel]); + goto bad; + } + + for (i = 0; i < WDC_NREG; i++) { + if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, + i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { + aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, + "couldn't subregion %s channel cmd regs\n", + cp->name); + goto bad; + } + } + wdc_init_shadow_regs(wdc_cp); + wdr->data32iot = wdr->cmd_iot; + wdr->data32ioh = wdr->cmd_iohs[0]; + return; + +bad: + cp->ata_channel.ch_flags |= ATACH_DISABLED; + return; +} + +#if NATA_DMA +void +pciide_cardbus_mapreg_dma(struct pciide_softc *sc, + struct cardbus_attach_args *ca) +{ + cardbus_devfunc_t ct = ca->ca_ct; + cardbus_chipset_tag_t cc = ct->ct_cc; + cardbus_function_tag_t cf = ct->ct_cf; + cardbusreg_t maptype; + bus_addr_t addr; + struct pciide_channel *pc; + int reg, chan; + bus_size_t size; + + /* + * Map DMA registers + * + * Note that sc_dma_ok is the right variable to test to see if + * DMA can be done. If the interface doesn't support DMA, + * sc_dma_ok will never be non-zero. If the DMA regs couldn't + * be mapped, it'll be zero. I.e., sc_dma_ok will only be + * non-zero if the interface supports DMA and the registers + * could be mapped. + * + * XXX Note that despite the fact that the Bus Master IDE specs + * XXX say that "The bus master IDE function uses 16 bytes of IO + * XXX space," some controllers (at least the United + * XXX Microelectronics UM8886BF) place it in memory space. + */ +#define CARDBUS_MAPREG_TYPE_MASK CARDBUS_MAPREG_TYPE_IO + maptype = cardbus_conf_read(cc, cf, ca->ca_tag, + PCIIDE_REG_BUS_MASTER_DMA) & CARDBUS_MAPREG_TYPE_MASK; + + switch (maptype) { + case CARDBUS_MAPREG_TYPE_IO: + sc->sc_dma_ok = (Cardbus_mapreg_map(ct, + PCIIDE_REG_BUS_MASTER_DMA, CARDBUS_MAPREG_TYPE_IO, 0, + &sc->sc_dma_iot, &sc->sc_dma_ioh, &addr, + &sc->sc_dma_size) == 0); + if (!sc->sc_dma_ok) { + aprint_verbose( + ", but unused (couldn't query registers)"); + break; + } + if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) + && addr >= 0x10000) { + sc->sc_dma_ok = 0; + Cardbus_mapreg_unmap(ct, PCIIDE_REG_BUS_MASTER_DMA, + sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_size); + aprint_verbose( + ", but unused (registers at unsafe address " + "%#lx)", (unsigned long)addr); + } + break; + + case CARDBUS_MAPREG_TYPE_MEM: + sc->sc_dma_ok = (Cardbus_mapreg_map(ct, + PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, &sc->sc_dma_iot, + &sc->sc_dma_ioh, NULL, &sc->sc_dma_size) == 0); + if (!sc->sc_dma_ok) + aprint_verbose(", but unused (couldn't map registers)"); + break; + + default: + sc->sc_dma_ok = 0; + aprint_verbose( + ", but unsupported register maptype (0x%x)", maptype); + } + + if (sc->sc_dma_ok) { + if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & + PCIIDE_OPTIONS_NODMA) { + aprint_verbose( + ", but unused (forced off by config file)"); + sc->sc_dma_ok = 0; + } + } + if (sc->sc_dma_ok == 0) + return; + + sc->sc_dmat = ca->ca_dmat; + sc->sc_wdcdev.dma_arg = sc; + sc->sc_wdcdev.dma_init = pciide_dma_init; + sc->sc_wdcdev.dma_start = pciide_dma_start; + sc->sc_wdcdev.dma_finish = pciide_dma_finish; + + /* + * Set up the default handles for the DMA registers. + * Just reserve 32 bits for each handle, unless space + * doesn't permit it. + */ + for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) { + pc = &sc->pciide_channels[chan]; + for (reg = 0; reg < IDEDMA_NREGS; reg++) { + size = 4; + if (size > (IDEDMA_SCH_OFFSET - reg)) + size = IDEDMA_SCH_OFFSET - reg; + if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, + IDEDMA_SCH_OFFSET * chan + reg, size, + &pc->dma_iohs[reg]) != 0) { + sc->sc_dma_ok = 0; + aprint_verbose( + ", but can't subregion offset %d size %lu", + reg, (u_long)size); + return; + } + } + } +} +#endif /* NATA_DMA */ + +/* some common code used by several chip channel_map */ +void +pciide_cardbus_mapchan(struct cardbus_attach_args *ca, + struct pciide_channel *cp, cardbusreg_t interface, + bus_size_t *cmdsizep, bus_size_t *ctlsizep, + int (*pci_intr)(void *)) +{ + struct ata_channel *wdc_cp = &cp->ata_channel; + + pciide_cardbus_mapregs_native(ca, cp, pci_intr); + wdcattach(wdc_cp); +} --- cardbus/pciide_cardbusvar.h.orig 1970-01-01 09:00:00.000000000 +0900 +++ cardbus/pciide_cardbusvar.h 2008-08-17 23:05:54.000000000 +0900 @@ -0,0 +1,53 @@ +/* $NetBSD: pciidevar.h,v 1.36 2008/01/04 00:27:27 joerg Exp $ */ + +/* + * Copyright (c) 1998 Christopher G. Demetriou. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Christopher G. Demetriou + * for the NetBSD Project. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DEV_CARDBUS_PCIIDE_CARDBUSVAR_H_ +#define _DEV_CARDBUS_PCIIDE_CARDBUSVAR_H_ + +void pciide_cardbus_common_attach(struct pciide_softc *, + struct cardbus_attach_args *, + const struct pciide_product_desc *); +int pciide_cardbus_common_detach(struct pciide_softc *, int); + +void pciide_cardbus_mapregs_native(struct cardbus_attach_args *, + struct pciide_channel *, + int (*pci_intr)(void *)); +void pciide_cardbus_mapreg_dma(struct pciide_softc *, + struct cardbus_attach_args *); +void pciide_cardbus_mapchan(struct cardbus_attach_args *, + struct pciide_channel *, cardbusreg_t, + bus_size_t *, bus_size_t *, + int (*pci_intr)(void *)); +void pciide_cardbus_map_compat_intr(struct cardbus_attach_args *, + struct pciide_channel *, int); + +#endif /* _DEV_CARDBUS_PCIIDE_CARDBUSVAR_H_ */