? pci/satalinkvar.h ? cardbus/pciide_cardbus_common.c ? cardbus/pciide_cardbusvar.h ? cardbus/satalink_cardbus.c Index: pci/pciide_common.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/pciide_common.c,v retrieving revision 1.38 diff -u -r1.38 pciide_common.c --- pci/pciide_common.c 18 Mar 2008 20:46:37 -0000 1.38 +++ pci/pciide_common.c 4 Aug 2008 03:35:26 -0000 @@ -106,6 +106,7 @@ 0, "Generic PCI IDE controller", default_chip_map, + NULL }; const struct pciide_product_desc * Index: pci/pciidevar.h =================================================================== RCS file: /cvsroot/src/sys/dev/pci/pciidevar.h,v retrieving revision 1.36 diff -u -r1.36 pciidevar.h --- pci/pciidevar.h 4 Jan 2008 00:27:27 -0000 1.36 +++ pci/pciidevar.h 4 Aug 2008 03:35:26 -0000 @@ -39,6 +39,7 @@ * Author: Christopher G. Demetriou, March 2, 1998. */ +#include #include #include #include @@ -78,6 +79,12 @@ struct wdc_softc sc_wdcdev; /* common wdc definitions */ pci_chipset_tag_t sc_pc; /* PCI registers info */ pcitag_t sc_tag; + cardbus_devfunc_t sc_ct; /* Cardbus registers info */ + cardbus_chipset_tag_t sc_cc; + cardbus_function_tag_t sc_cf; + cardbustag_t sc_ctag; + bus_size_t sc_cmdsize[PCIIDE_NUM_CHANNELS]; + bus_size_t sc_ctlsize[PCIIDE_NUM_CHANNELS]; void *sc_pci_ih; /* PCI interrupt handle */ #if NATA_DMA int sc_dma_ok; /* bus-master DMA info */ @@ -90,6 +97,7 @@ */ bus_space_tag_t sc_dma_iot; bus_space_handle_t sc_dma_ioh; + bus_size_t sc_dma_size; bus_dma_tag_t sc_dmat; /* @@ -115,7 +123,10 @@ */ bus_space_tag_t sc_ba5_st; bus_space_handle_t sc_ba5_sh; + bus_size_t sc_ba5_ssize; int sc_ba5_en; + uint32_t (*sc_ba5_read_4)(struct pciide_softc *, bus_addr_t); + void (*sc_ba5_write_4)(struct pciide_softc *, bus_addr_t, uint32_t); #endif /* NATA_DMA */ /* Vendor info (for interpreting Chip description) */ @@ -165,6 +176,8 @@ const char *ide_name; /* map and setup chip, probe drives */ void (*chip_map)(struct pciide_softc*, struct pci_attach_args*); + void (*cardbus_chip_map)(struct pciide_softc*, + struct cardbus_attach_args*); }; /* Flags for ide_flags */ Index: pci/satalink.c =================================================================== RCS file: /cvsroot/src/sys/dev/pci/satalink.c,v retrieving revision 1.38 diff -u -r1.38 satalink.c --- pci/satalink.c 28 Apr 2008 20:23:55 -0000 1.38 +++ pci/satalink.c 4 Aug 2008 03:35:26 -0000 @@ -41,6 +41,7 @@ #include #include #include +#include #include #include @@ -49,46 +50,7 @@ /* * Register map for BA5 register space, indexed by channel. */ -static const struct { - bus_addr_t ba5_IDEDMA_CMD; - bus_addr_t ba5_IDEDMA_CTL; - bus_addr_t ba5_IDEDMA_TBL; - bus_addr_t ba5_IDEDMA_CMD2; - bus_addr_t ba5_IDEDMA_CTL2; - bus_addr_t ba5_IDE_TF0; - bus_addr_t ba5_IDE_TF1; - bus_addr_t ba5_IDE_TF2; - bus_addr_t ba5_IDE_TF3; - bus_addr_t ba5_IDE_TF4; - bus_addr_t ba5_IDE_TF5; - bus_addr_t ba5_IDE_TF6; - bus_addr_t ba5_IDE_TF7; - bus_addr_t ba5_IDE_TF8; - bus_addr_t ba5_IDE_RAD; - bus_addr_t ba5_IDE_TF9; - bus_addr_t ba5_IDE_TF10; - bus_addr_t ba5_IDE_TF11; - bus_addr_t ba5_IDE_TF12; - bus_addr_t ba5_IDE_TF13; - bus_addr_t ba5_IDE_TF14; - bus_addr_t ba5_IDE_TF15; - bus_addr_t ba5_IDE_TF16; - bus_addr_t ba5_IDE_TF17; - bus_addr_t ba5_IDE_TF18; - bus_addr_t ba5_IDE_TF19; - bus_addr_t ba5_IDE_RABC; - bus_addr_t ba5_IDE_CMD_STS; - bus_addr_t ba5_IDE_CFG_STS; - bus_addr_t ba5_IDE_DTM; - bus_addr_t ba5_SControl; - bus_addr_t ba5_SStatus; - bus_addr_t ba5_SError; - bus_addr_t ba5_SActive; /* 3114 */ - bus_addr_t ba5_SMisc; - bus_addr_t ba5_PHY_CONFIG; - bus_addr_t ba5_SIEN; - bus_addr_t ba5_SFISCfg; -} satalink_ba5_regmap[] = { +const struct satalink_ba5_regmap satalink_ba5_regmap[] = { { /* Channel 0 */ .ba5_IDEDMA_CMD = 0x000, .ba5_IDEDMA_CTL = 0x002, @@ -251,46 +213,49 @@ }, }; -#define ba5_SIS 0x214 /* summary interrupt status */ - -/* Interrupt steering bit in BA5[0x200]. */ -#define IDEDMA_CMD_INT_STEER (1U << 1) - static int satalink_match(device_t, cfdata_t, void *); static void satalink_attach(device_t, device_t, void *); CFATTACH_DECL_NEW(satalink, sizeof(struct pciide_softc), satalink_match, satalink_attach, NULL, NULL); +static uint32_t ba5_read_4(struct pciide_softc *, bus_addr_t); +static void ba5_write_4(struct pciide_softc *, bus_addr_t, uint32_t); + static void sii3112_chip_map(struct pciide_softc*, struct pci_attach_args*); static void sii3114_chip_map(struct pciide_softc*, struct pci_attach_args*); -static void sii3112_drv_probe(struct ata_channel*); -static void sii3112_setup_channel(struct ata_channel*); +void sii3112_drv_probe(struct ata_channel*); +void sii3112_setup_channel(struct ata_channel*); -static const struct pciide_product_desc pciide_satalink_products[] = { +const struct pciide_product_desc pciide_satalink_products[] = { { PCI_PRODUCT_CMDTECH_3112, 0, "Silicon Image SATALink 3112", sii3112_chip_map, + sii3112_cardbus_chip_map, }, { PCI_PRODUCT_CMDTECH_3512, 0, "Silicon Image SATALink 3512", sii3112_chip_map, + sii3112_cardbus_chip_map, }, { PCI_PRODUCT_CMDTECH_AAR_1210SA, 0, "Adaptec AAR-1210SA serial ATA RAID controller", sii3112_chip_map, + sii3112_cardbus_chip_map, }, { PCI_PRODUCT_CMDTECH_3114, 0, "Silicon Image SATALink 3114", sii3114_chip_map, + sii3114_cardbus_chip_map, }, { 0, 0, NULL, + NULL, NULL } }; @@ -314,6 +279,8 @@ struct pciide_softc *sc = device_private(self); sc->sc_wdcdev.sc_atac.atac_dev = self; + sc->sc_ba5_read_4 = ba5_read_4; + sc->sc_ba5_write_4 = ba5_write_4; pciide_common_attach(sc, pa, pciide_lookup_product(pa->pa_id, pciide_satalink_products)); @@ -334,7 +301,7 @@ return (rv); } -static inline uint32_t +static uint32_t ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) { @@ -344,9 +311,6 @@ return (ba5_read_4_ind(sc, reg)); } -#define BA5_READ_4(sc, chan, reg) \ - ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg) - static inline void ba5_write_4_ind(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) { @@ -358,7 +322,7 @@ splx(s); } -static inline void +static void ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) { @@ -368,9 +332,6 @@ ba5_write_4_ind(sc, reg, val); } -#define BA5_WRITE_4(sc, chan, reg, val) \ - ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val)) - /* * When the Silicon Image 3112 retries a PCI memory read command, * it may retry it as a memory read multiple command under some @@ -568,7 +529,7 @@ sc->sc_dma_ok = 1; } -static int +int sii3114_chansetup(struct pciide_softc *sc, int channel) { static const char *channel_names[] = { @@ -603,7 +564,7 @@ return (1); } -static void +void sii3114_mapchan(struct pciide_channel *cp) { struct ata_channel *wdc_cp = &cp->ata_channel; @@ -775,7 +736,7 @@ /* Probe the drives using SATA registers. * Note we can't use wdc_sataprobe as we may not be able to map ba5 */ -static void +void sii3112_drv_probe(struct ata_channel *chp) { struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); @@ -886,7 +847,7 @@ } } -static void +void sii3112_setup_channel(struct ata_channel *chp) { struct ata_drive_datas *drvp; Index: cardbus/files.cardbus =================================================================== RCS file: /cvsroot/src/sys/dev/cardbus/files.cardbus,v retrieving revision 1.34 diff -u -r1.34 files.cardbus --- cardbus/files.cardbus 7 Sep 2006 14:22:07 -0000 1.34 +++ cardbus/files.cardbus 4 Aug 2008 03:35:26 -0000 @@ -131,3 +131,15 @@ # attach njata at cardbus with njata_cardbus file dev/cardbus/njata_cardbus.c njata_cardbus + +# +# PCI IDE controllers +# +define pciide_cardbus_common +file dev/cardbus/pciide_cardbus_common.c pciide_cardbus_common + +# +# Silicon Image SATALink controllers +# +attach satalink at cardbus with satalink_cardbus: pciide_cardbus_common +file dev/cardbus/satalink_cardbus.c satalink_cardbus